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Ken C Mui

from Portland, OR
Age ~69

Ken Mui Phones & Addresses

  • 3695 Poehler Ter, Portland, OR 97229 (503) 439-6997
  • Davis, CA
  • Concord, CA
  • 14924 Opal Dr, Beaverton, OR 97007
  • Walnut Creek, CA
  • San Jose, CA
  • Canyon Country, CA

Work

Company: Bhg j f finnegan realtors Address: 362 Gellert Blvd, Daly City, CA 94015 Industries: Real Estate Agents and Managers

Professional Records

Real Estate Brokers

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Ken Mui, Daly City CA Agent

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Work:
BHF-JF Finnegan Realtors
Daly City, CA
(415) 341-7214 (Phone)
Ken Mui Photo 2

Ken Mui, San Francisco CA Agent

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Work:
Prudential California Realty
San Francisco, CA
(415) 341-7214 (Phone)

Resumes

Resumes

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Ken Mui

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Location:
6213 Brittany Ave, Newark, CA 94560
Industry:
Semiconductors
Work:
Idt - Integrated Device Technology, Inc. 1995 - 2012
Member of Technical Staff

Pericom Semiconductor Jul 1993 - Feb 1995
Project Manager
Education:
Rutgers University 1978 - 1984
Doctorates, Doctor of Philosophy, Physics, Philosophy
Skills:
Process Integration
Device Physics
Design Rule
Test Pattern Design
Sram Process
Dram Process
Tcl/Tk
Languages:
English
Mandarin
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Ken Mui

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Ken Mui

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Ken Mui

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Ken Mui

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Ken Mui

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Ken Mui

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Business Records

Name / Title
Company / Classification
Phones & Addresses
Ken Mui
Bhg J F Finnegan Realtors
Real Estate Agents and Managers
362 Gellert Blvd, Daly City, CA 94015
Ken Mui
Principal
Kenji Construction
Single-Family House Construction
62 Crane St, San Francisco, CA 94124
Ken Mui
Bhg J F Finnegan Realtors
362 Gellert Blvd, Daly City, CA 94015
(650) 757-0888
Ken Mui
Bhg J F Finnegan Realtors
Real Estate Agents and Managers
362 Gellert Blvd, Daly City, CA 94015

Publications

Us Patents

Process For Forming Cmos Devices Using Removable Spacers

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US Patent:
7544556, Jun 9, 2009
Filed:
Nov 12, 2004
Appl. No.:
10/986636
Inventors:
Ken Mui - Portland OR, US
Aaron Marmorstein - Atlanta GA, US
Eric Lee - Corvallis OR, US
Assignee:
Integrated Device Technology, Inc. - San Jose CA
International Classification:
H01L 21/8238
US Classification:
438199, 438230, 438585, 438305
Abstract:
A process for forming CMOS devices is disclosed in which disposable spacers are used to obtain a structure having improved gap-fill characteristics. First, gate film stacks are formed on the substrate. A shallow implant process is performed so as to form shallow source/drain implant regions. A layer of oxide and a layer of silicon nitride are deposited and etched to form a first set of spacers that extend on opposite sides of the gate film stacks. A second implant is performed so as to form intermediate source/drain implant regions. A set of disposable spacers are then formed that extend on opposite sides of each of the gate film stacks. A third implant process is performed so as to form deep source/drain implant regions. The disposable spacers are then removed, providing more space for the subsequently-formed contact to land.
Ken C Mui from Portland, OR, age ~69 Get Report