Jun A Tang

8102791, Jan 24, 2012

Jul 25, 2008

12/179599

Jun Tang - Lake Forest CA, US

Newport Media, Inc. - Lake Forest CA

H04J 11/00

370312

Address generation for interleaving in a wireless communication system includes at least one input generation module to generate at least one input signal. A first address generator module and a second address generator module generate a first output address for interleaving and a second output address for interleaving. A selector module selects an address for interleaving from the first and the second output address based on predetermined criteria. At least one input translation module is receives an input signal and translate the received input signal to generate a nominal input signal based on a value of the received input signal. An address generation module generates an address for interleaving based on the nominal input signal.

8482675, Jul 9, 2013

Sep 30, 2010

12/894789

James Carwana - Aliso Viejo CA, US
Jun Tang - Lake Forest CA, US
Philip Treigherman - Newport Beach CA, US
Chaoliang T. Chen - Irvine CA, US
Tracy Denk - Aliso Viejo CA, US

Newport Media, Inc. - Lake Forest CA

H04N 5/44
H04N 5/45

348725, 348565

A multi-chip antenna diversity architecture and method includes a first receiver chip that receives a first input signal from a first antenna. The first receiver chip includes a first tuner that amplifies the first input signal, a crystal operatively connected to a first crystal oscillator circuit, and a first crystal oscillator clock buffer that receives a clock signal from the first crystal oscillator circuit. A first demodulator demodulates the input signal received from the first tuner. A second receiver chip receives a second input signal from a second antenna. The second receiver chip includes a second crystal oscillator circuit, a second crystal oscillator clock buffer, a second tuner, and a second demodulator that receives diversity data from the first demodulator. The first crystal oscillator clock buffer drives the clock signal to the second crystal oscillator clock buffer, the second tuner, and the second demodulator of the second receiver chip.

20120063380, Mar 15, 2012

Nov 21, 2011

13/300817

Jun Tang - Lake Forest CA, US

NEWPORT MEDIA, INC. - Lake Forest CA

H04W 4/06

370312

Address generation for interleaving in a wireless communication system includes at least one input generation module to generate at least one input signal. A first address generator module and a second address generator module generate a first output address for interleaving and a second output address for interleaving. A selector module selects an address for interleaving from the first and the second output address based on predetermined criteria. At least one input translation module is receives an input signal and translate the received input signal to generate a nominal input signal based on a value of the received input signal. An address generation module generates an address for interleaving based on the nominal input signal.

20130271662, Oct 17, 2013

May 21, 2013

13/899311

James Carwana - Aliso Viejo CA, US
Jun Tang - Irvine CA, US
Philip Treigherman - Newport Beach CA, US
Chaoliang T. Chen - Tustin CA, US
Tracy Denk - Aliso Viejo CA, US

NEWPORT MEDIA, INC. - Lake Forest CA

H04N 5/45

348565

A multi-chip antenna diversity architecture and method includes a first receiver chip that receives a first input signal from a first antenna. The first receiver chip includes a first tuner that amplifies the first input signal, a crystal operatively connected to a first crystal oscillator circuit, and a first crystal oscillator clock buffer that receives a clock signal from the first crystal oscillator circuit. A first demodulator demodulates the input signal received from the first tuner. A second receiver chip receives a second input signal from a second antenna. The second receiver chip includes a second crystal oscillator circuit, a second crystal oscillator clock buffer, a second tuner, and a second demodulator that receives diversity data from the first demodulator. The first crystal oscillator clock buffer drives the clock signal to the second crystal oscillator clock buffer, the second tuner, and the second demodulator of the second receiver chip.