Jun I Kim

6342800, Jan 29, 2002

Oct 26, 2000

09/698997

Donald C. Stark - Palo Alot CA
Jun Kim - Redwood City CA
Kurt T. Knorpp - San Carlos CA
Michael Tak-Kei Ching - Sunnyvale CA
Natsuki Kushiyama - Yokohama, JP

Rambus Inc. - Los Altos CA

H03K 512

327170, 327175

An output driver has an output multiplexor and an output current driver. The output multiplexor receives a data signal and outputs a q-node signal. The output current driver receives the q-node signal and drives a bus based on the q-node signal. The output multiplexor processes the data signal in various ways to generate the q-node signal. The output current driver is responsive to current control bits to select a amount of output drive current. In addition, the output multiplexor is controlled such that the output impedance of the output current driver is maintained within a predetermined range.

6539072, Mar 25, 2003

Mar 13, 2000

09/524402

Kevin S. Donnelly - San Francisco CA
Pak Shing Chau - San Jose CA
Mark A. Horowitz - Palo Alto CA
Thomas H. Lee - Cupertino CA
Mark G. Johnson - Los Altos CA
Benedict C. Lau - San Jose CA
Leung Yu - Santa Clara CA
Bruno W. Garlepp - Mountain View CA
Yiu-Fai Chan - Los Altos Hills CA
Jun Kim - Redwood City CA
Chanh Vi Tran - San Jose CA
Donald C. Stark - Palo Alto CA
Nhat M. Nguyen - San Jose CA

Rambus, Inc. - Los Altos CA

H04L 700

375371, 375358, 375373, 327158

Delay locked loop circuitry for generating a predetermined phase relationship between a pair of clocks. A first delay-locked loop includes a delay elements arranged in a chain, the chain receiving an input clock and generating, from each delay element, a set of phase vectors, each shifted a unit delay from the adjacent vector. The first delay-locked loop adjusts the unit delays in the delay chain using a delay adjustment signal so that the phase vectors span a predetermined phase shift of the input clock. A second delay-locked loop selects, from the first delay-locked loop, a pair of phase vectors which brackets the phase of an input clock. A phase interpolator receives the selected pair of vectors and generates an output clock and a delayed output clock, the amount of the delay being controlled by the delay adjustment signal of the first delay-locked loop circuitry. A phase detector compares the delayed output clock with the input clock and adjusts the phase interpolator, based on the phase comparison, so that the phase of the delayed output clock is in phase with the input clock. As a result, there is a predetermined phase relationship between the output clock and the input clock, the phase relationship being the amount of delay between the output clock and the delayed output clock.

6643787, Nov 4, 2003

Oct 19, 1999

09/421073

Jared LeVan Zerbe - Woodside CA
Kevin S. Donnelly - Los Altos CA
Stefanos Sidiropoulos - Palo Alto CA
Donald C. Stark - Los Altos CA
Mark A. Horowitz - Menlo Park CA
Leung Yu - Los Altos CA
Roxanne Vu - San Jose CA
Jun Kim - Redwood City CA
Bruno W. Garlepp - Sunnyvale CA
Benedict Chung-Kwong Lau - San Jose CA

Rambus Inc. - Los Altos CA

G06F 1340

713400, 710104

A bus system comprising a master connected to one or more slave devices via a bus is disclosed. The bus system is able to effectively communicate control information during a calibration phase and to individually determine appropriate timing and/or voltage offsets for each slave device. The offsets are used to optimize transfer timing (including duty cycle characteristics), signal equalization, and voltage levels for data exchanged between the master and the slave devices.

6661268, Dec 9, 2003

Dec 11, 2001

10/014650

Donald C. Stark - Palo Alto CA
Jun Kim - Redwood City CA
Kurt T. Knorpp - San Carlos CA
Michael Tak-Kei Ching - Sunnyvale CA
Natsuki Kushiyama - Yokohama, JP

Rambus Inc. - Los Altos CA

H03K 512

327170, 327538

An output driver has an output multiplexor and an output current driver. The output multiplexor receives a data signal and outputs a q-node signal. The output current driver receives the q-node signal and drives a bus based on the q-node signal. The output multiplexor processes the data signal in various ways to generate the q-node signal. The output current driver is responsive to current control bits to select a amount of output drive current. In addition, the output multiplexor is controlled such that the output impedance of the output current driver is maintained within a predetermined range.

6922092, Jul 26, 2005

Dec 8, 2003

10/731718

Donald C. Stark - Palo Alto CA, US
Jun Kim - Redwood City CA, US
Kurt T. Knorpp - San Carlos CA, US
Michael Tak-Kei Ching - Sunnyvale CA, US
Natsuki Kushiyama - Yokohama, JP

Rambus Inc. - Los Altos CA

H03K005/12

327170, 327538

An output driver has an output multiplexor and an output current driver. The output multiplexor receives a data signal and outputs a q-node signal. The output current driver receives the q-node signal and drives a bus based on the q-node signal. The output multiplexor processes the data signal in various ways to generate the q-node signal. The output current driver is responsive to current control bits to select a amount of output drive current. In addition, the output multiplexor is controlled such that the output impedance of the output current driver is maintained within a predetermined range.

6950956, Sep 27, 2005

Nov 3, 2003

10/700655

Jared LeVan Zerbe - Woodside CA, US
Kevin S. Donnelly - Los Altos CA, US
Stefanos Sidiropoulos - Palo Alto CA, US
Donald C. Stark - Los Altos CA, US
Mark A. Horowitz - Menlo Park CA, US
Leung Yu - Los Altos CA, US
Roxanne Vu - San Jose CA, US
Jun Kim - Redwood City CA, US
Bruno W. Garlepp - Sunnyvale CA, US
Benedict Chung-Kwong Lau - San Jose CA, US

Rambus Inc. - Los Altos CA

G06F001/12

713400, 713375, 713401, 713500, 713503, 713600, 327 2, 327 9, 327141, 327233, 375147, 375149, 375219, 375316, 37524028

An integrated circuit device includes a receiver, a register and a clock circuit. The receiver samples data from an external signal line in response to an internal clock signal. The register stores a value that represents a timing offset to adjust the time at which the data is sampled. The clock circuit generates the internal clock signal such that the internal clock signal maintains a controlled timing relationship with respect to an external clock signal. The clock circuit includes an interpolator that phase mixes a set of reference clock signals such that the internal clock signal is phase offset in accordance with the value.

6987823, Jan 17, 2006

Feb 7, 2000

09/499025

Donald C. Stark - Los Altos Hills CA, US
Jun Kim - Redwood City CA, US
Stefanos Sidiropoulos - Palo Alto CA, US

Rambus Inc. - Los Altos CA

H04L 7/00

375354, 370503, 327141

A circuit defining a second system clock in a system comprising a master connected to one or more slave devices via a channel, the channel communicating an externally generated first system clock towards the master. The circuit comprising a delay locked loop circuit configured to receive the first system clock and a second phase feedback signal as inputs and to generate a transmit clock signal. A 90 degrees block configured to receive the transmit system clock and to generate a 90 degrees phased shifted version of the transmit clock signal. An output driver circuit configured to receive the 90 degrees phased shifted version of the transmit clock signal and to generate the second system clock. A first phase detector configured to receive a receive system clock and the transmit system clock and to generate a first phase feedback signal. A delay element configured to receive the first system clock and the first phase feedback signal and to generate a delayed first system clock.

7039147, May 2, 2006

Feb 14, 2003

10/366865

Kevin S. Donnelly - San Francisco CA, US
Pak Shing Chau - San Jose CA, US
Mark A. Horowitz - Palo Alto CA, US
Thomas H. Lee - Cupertino CA, US
Mark G. Johnson - Los Altos CA, US
Benedict C. Lau - San Jose CA, US
Leung Yu - Santa Clara CA, US
Bruno W. Garlepp - Mountain View CA, US
Yiu-Fai Chan - Los Altos Hills CA, US
Jun Kim - Redwood City CA, US
Chanh Vi Tran - San Jose CA, US
Donald C. Stark - Palo Alto CA, US
Nhat M. Nguyen - San Jose CA, US

Rambus Inc. - Los Altos CA

H03D 3/24

375373

Delay locked loop circuitry for generating a predetermined phase relationship between a pair of clocks. A first delay-locked loop includes a delay elements arranged in a chain, the chain receiving an input clock and generating, from each delay element, a set of phase vectors, each shifted a unit delay from the adjacent vector. The first delay-locked loop adjusts the unit delays in the delay chain using a delay adjustment signal so that the phase vectors span a predetermined phase shift of the input clock. A second delay-locked loop selects, from the first delay-locked loop, a pair of phase vectors which brackets the phase of an input clock. A phase interpolator receives the selected pair of vectors and generates an output clock and a delayed output clock, the amount of the delay being controlled by the delay adjustment signal of the first delay-locked loop circuitry. A phase detector compares the delayed output clock with the input clock and adjusts the phase interpolator, based on the phase comparison, so that the phase of the delayed output clock is in phase with the input clock. As a result, there is a predetermined phase relationship between the output clock and the input clock, the phase relationship being the amount of delay between the output clock and the delayed output clock.