Jong Woo Lee

6728140, Apr 27, 2004

Dec 5, 2001

10/011157

Kyung Joon Han - Palo Alto CA
Joo Weon Park - Pleasanton CA
Dung Tran - San Jose CA
Steve K. Hsia - San Jose CA
Jong Seuk Lee - Palo Alto CA
Dae Hyun Kim - Fremont CA

NexFlash Technologies, Inc. - San Jose CA

G11C 1604

36518524, 36518526, 3651853, 36518529

A convergence signal includes a series of voltage pulses used to perform a convergence procedure in one or more flash EEPROM memory cells (transistors). In one instance subsequent voltage pulses in the convergence signal each have a higher voltage than the preceding pulse. In another instance, subsequent voltage pulses in the convergence signal each have a longer duration than the preceding pulse. An integrated circuit includes an array of memory cells and an erase control unit which controls the application of the convergence signal to one or more memory cells. The integrated circuit may be either serial or parallel flash EEPROM in which bulk, sector, or page mode erasing is used.

6795957, Sep 21, 2004

Dec 18, 2002

10/323398

Glenn Lai - Milpitas CA
Jong Chang Lee - Macungie PA

Cadence Design Systems, Inc. - San Jose CA

G06F 1750

716 12, 716 8

An IC layout tool determines areas of an IC layout in which to provide power wire interconnection vias by first querying a âworldâ HV tree keeping track of power wires and other objects within the IC layout to determine areas of overlap between power wires residing on differing layers of the layout. The layout tool then creates a separate via HV tree identifying positions of âvia boxesâ residing on areas of each layer of the IC between overlapping power wires. The tool manipulates the data stored in the via HV tree to partition and merge adjacent via boxes residing on each layer as necessary to produce via boxes indicating positions of a set of unobstructed, rectangular areas of each layer of the layout in which vias may be placed to interconnect overlapping power wires. The IC layout tool then places vias in each rectangular area of each layer the via HV tree indicates is being occupied by via boxes.

6826080, Nov 30, 2004

May 24, 2002

10/154979

Joo Weon Park - Pleasanton CA
Kyung Joon Han - Palo Alto CA
Jong Seuk Lee - Palo Alto CA

NexFlash Technologies, Inc. - San Jose CA

G11C 1604

36518505, 36518511, 36518516, 36518533

In nonvolatile memory cell array, the memory cells of each sector are organized into groups of successive cells, the groups preferably being of the same size and preferably isolated from one another in both the row and column directions by a suitable isolation structure such as field dielectric or trench dielectric. Because of cell group isolation, each group of column lines may be decoded by its own relatively small program column select, which preferably is replicated in essentially identical form for all groups of column lines. While each program column select preferably is used to decode one group of column lines, larger program column selects may be used if desired to decode two or more groups of column lines. Read column selects may decode one or more groups of column lines as desired. The number of column lines decoded may the same as or different than the number of column lines decoded.

6873004, Mar 29, 2005

Feb 4, 2003

10/358645

Kyung Joon Han - Palo Alto CA, US
Steve K. Hsia - San Jose CA, US
Joo Weon Park - Pleasanton CA, US
Jong Seuk Lee - Palo Alto CA, US

NexFlash Technologies, Inc. - San Jose CA

H01L029/788

257315, 257E293, 257 6, 438266, 438286, 438302, 438525

An asymmetrical virtual ground single transistor floating gate memory cell has a floating gate that overlies a channel region in a p-well, the channel region lying between a heavily doped n+ drain region and a lightly doped n− source region. A heavily doped p+ region known as a “halo” is disposed in the channel adjacent the heavily doped n+ drain. The floating gate is spaced away from the channel region by a generally thin tunnel oxide. A lightly doped source with a graded source/channel junction reduces source side CHE generation. In one variation, a thicker oxide between the source and the floating gate reduces CHE injection from the source side. A heavily doped drain with a halo implant in the channel adjacent the drain enhances drain side CHE generation.

7094089, Aug 22, 2006

Mar 12, 2004

10/799403

Bartley K. Andre - Menlo Park CA, US
Jonathan P. Ive - San Francisco CA, US
Jong Min Lee - San Francisco CA, US
Kan Lim - Sunnyvale CA, US

Apple Computer, Inc. - Cupertino CA

H01R 21/00

439218, 439607

A DC connector arrangement is disclosed. The DC connector arrangement includes a DC plug and a DC receptacle that are configured to engage one another at more than one position. The DC plug and DC receptacle are also configured with a small contact distance to minimize the insertion and extraction forces that occur between the DC plug and the DC receptacle.

7558900, Jul 7, 2009

Mar 11, 2005

11/078205

Robin J. Jigour - San Jose CA, US
Eungjoon Park - Fremont CA, US
Joo Weon Park - Pleasanton CA, US
Jong Seuk Lee - Palo Alto CA, US

Winbound Electronics Corporation - Hisn Chu

G06F 13/14
G06F 3/00
G06F 13/42

710305, 710 11, 710105

A serial flash memory is provided with multiple configurable pins, at least one of which is selectively configurable for use in either single-bit serial data transfers or multiple-bit serial data transfers. In single-bit serial mode, data transfer is bit-by-bit through a pin. In multiple-bit serial mode, a number of sequential bits are transferred at a time through respective pins. The serial flash memory may have 16 or fewer pins, and even 8 or fewer pins, so that low pin count packaging such as the 8-pin or 16-pin SOIC package and the 8-contact MLP/QFN/SON package may be used. The availability of the single-bit serial type protocol enables compatibility with a number of existing systems, while the availability of the multiple-bit serial type protocol enables the serial flash memory to provide data transfer rates, in systems that can support them, that are significantly faster than available with standard serial flash memories.

8380747, Feb 19, 2013

Oct 27, 2008

12/258793

Ross Dargahi - Mountain View CA, US
Kevin M. Henrikson - San Mateo CA, US
Roland J. Schemers - Emerald Hills CA, US
Jong Yoon Lee - Mountain View CA, US

VMware, Inc. - Palo Alto CA

G06F 17/30

707796, 709217

The present invention is, in one embodiment, a system and method based on a client-server architecture for seamlessly integrating various information systems. In one embodiment, a bundle of files is deployed to a collaboration client, in order to enable the integration of the collaboration client with disparate information systems and content. In one embodiment, content within a mailbox item is allowed to become a “live” object, and is associated with trigger events, and actions, including sending all or part of the content to a separate information system. In one embodiment, mailbox items are subjected to predefined searches to assess whether they include certain content objects. In another embodiment, panel item elements are visible in the overview panel of the collaboration client. The user may interact with the panel items by dragging content onto them, double clicking them, and invoking actions from a context menu if one is available.

8565422, Oct 22, 2013

Aug 9, 2011

13/206194

Jong Lee - Pleasanton CA, US
Charles Mortimore - San Francisco CA, US

salesforce.com, inc. - San Francisco CA

G06F 21/00

380 44, 726 3, 726 9, 713167, 713168, 713189, 380 45, 380277, 705 57

Various techniques and procedures related to encryption key versioning and rotation in a multi-tenant environment are presented here. One approach employs a computer-implemented method of managing encrypted data and their associated encryption keys. In accordance with this approach, a key splitting process securely stores a master key used to encrypt tenant-level encryption keys, a key versioning process is used to securely track updated encryption keys, and a key rotation process is used to rotate encrypted data to an updated version of a tenant-level encryption key.