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John D Deforge

from Barre, VT
Deceased
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Also known as:
John Living Deforge, John Scott Deforge, John S Deforge, John B Deforge, John Daniel Forge, John Scott Forge, John D Forge, John De
Related to:
Nick DecarloMichael Scott Deforge, 31Stephen G ScottBarbara L Deforge, 71Jacqueline J Scott, 55Helen S DeforgeJeremy Alan Hart, 49Sandra L De Forge, 71Daniel R Deforge, 64
Connected to:
Carolyn J Deforge, 71Christian Deforge, 54Debora Deforge, 63Dennis E Deforge, 45Gerard P Deforge, 71Joanne M Deforge, 77Kimberly J Deforge, 52Linda L Deforge, 58Michael J Deforge, 50Mindy Deforge, 37

John Deforge Phones & Addresses

  • Barre, VT
  • New Sharon, ME
  • West Danville, VT
  • North Lawrence, NY
  • 630 137Th St, Bradenton, FL 34201 (941) 741-2022
  • 198 49Th St W, Bradenton, FL 34209
  • 8220 Natures Way, Lakewood Ranch, FL 34202 (941) 907-1278
  • Tampa, FL
  • Holmes Beach, FL
  • Manasota, FL

Resumes

Resumes

John Deforge Photo 1

N And A

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Location:
Barre, VT
Industry:
Food Production
Work:

N and A
John Deforge Photo 2

John Deforge

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John Deforge Photo 3

John Deforge

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Publications

Us Patents

Electrical Mask Identification Of Memory Modules

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US Patent:
6570254, May 27, 2003
Filed:
May 31, 2001
Appl. No.:
09/871087
Inventors:
John B. DeForge - Barre VT
David E. Douse - Hinesburg VT
Steven M. Eustis - Essex Junction VT
Erik L. Hedberg - Essex Junction VT
Susan M. Litten - Jericho VT
Endre P. Thoma - Colchester VT
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 2348
US Classification:
257758
Abstract:
Mask programmable conductors of the same construction as the mask layers they define are utilized for mask vintage identification. When the actual mask layer is altered, the change is recorded within the mask itself. Mask identification can be fabricated to identify the following type of mask layers: DTâdeep trench; SSâsurface strap; DIFFâDiffusion; NDIFFâN Diffusion; PDIFFâP Diffusion; WLâN wells; PCâpolysilicon gates; BNâN diffusion Implant; BPâP diffusion Implant; C âfirst contact; M âfirst metal layer; C âsecond contact; and, M2âsecond metal layer. Conducting paths that incorporate, in series, the mask programmable conductor technology devices are: M -C -PC-C -DIFF-C -M -C -M ; M -C -PDIFF-SS-DT-SS-PDIFF-C -M -C -M ; M -C -M -C -PC-C -M ; M -C -M -C -NDIFF-WL-NDIFF-C -M ; and, M -C -M -C -NDIFF-C -M -C -PC-C -M. These conducting paths are electrically opened with the omission of any of the layers in the series path.

Creating Deep Trenches On Underlying Substrate

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US Patent:
8586444, Nov 19, 2013
Filed:
Mar 23, 2012
Appl. No.:
13/428004
Inventors:
Jennifer E. Appleyard - Burlington VT, US
John B. DeForge - Barre VT, US
Herbert L. Ho - New Windsor NY, US
Babar A. Khan - Ossining NY, US
Kirk D. Peterson - Jericho VT, US
Andrew A. Turner - Underhill VT, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 21/20
US Classification:
438392, 438249, 438244, 438387
Abstract:
A semiconductor structure and method of fabricating the same are disclosed. In an embodiment, the structure includes a first substrate having a buried plate or plates in the substrate. Each buried plate includes at least one buried plate contact, and a plurality of deep trench capacitors disposed about the at least one buried plate contact. A first oxide layer is disposed over the first substrate. The deep trench capacitors and buried plate contacts in the first substrate may be accessed for use in a variety of memory and decoupling applications.

Creating Deep Trenches On Underlying Substrate

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US Patent:
20140021585, Jan 23, 2014
Filed:
Sep 25, 2013
Appl. No.:
14/036474
Inventors:
John E. Barth - Williston VT, US
John B. DeForge - Barre VT, US
Herbert L. Ho - Cornwall NY, US
Babar A. Khan - Ossining NY, US
Kirk D. Peterson - Jericho VT, US
Andrew A. Turner - Underhill VT, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 49/02
US Classification:
257532
Abstract:
A semiconductor structure and method of fabricating the same are disclosed. In an embodiment, the structure includes a first substrate having a buried plate or plates in the substrate. Each buried plate includes at least one buried plate contact, and a plurality of deep trench capacitors disposed about the at least one buried plate contact. A first oxide layer is disposed over the first substrate. The deep trench capacitors and buried plate contacts in the first substrate may be accessed for use in a variety of memory and decoupling applications.

Electrical Mask Identification Of Memory Modules

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US Patent:
62682288, Jul 31, 2001
Filed:
Jan 27, 1999
Appl. No.:
9/238874
Inventors:
John B. DeForge - Barre VT
David E. Douse - Hinesburg VT
Steven M. Eustis - Essex Junction VT
Erik L. Hedberg - Essex Junction VT
Susan M. Litten - Jericho VT
Endre P. Thoma - Colchester VT
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 2166
US Classification:
438 18
Abstract:
Mask programmable conductors of the same construction as the mask layers they define are utilized for mask vintage identification. When the actual mask layer is altered, the change is recorded within the mask itself. Mask identification can be fabricated to identify the following type of mask layers: DT--deep trench; SS--surface strap; DIFF--Diffusion; NDIFF--N Diffusion; PDIFF--P Diffusion; WL--N wells; PC--polysilicon gates; BN--N diffusion Implant; BP--P diffusion Implant; C1--first contact; M1--first metal layer; C2--second contact; and, M2--second metal layer. Conducting paths that incorporate, in series, the mask programmable conductor technology devices are: M1-C1-PC-C1-DIFF-C1-M1-C2-M2; M1-C1-PDIFF-SS-DT-SS-PDIFF-C1-M1-C2-M2; M2-C2-M1-C1-PC-C1-M1; M2-C2-M1-C1-NDIFF-WL-NDIFF-C1-M1; and, M2-C2-M1-C1-NDIFF-C1-M1-C1-PC-C1-M1. These conducting paths are electrically opened with the omission of any of the layers in the series path.

Microchip Level Shared Array Repair

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US Patent:
20210319845, Oct 14, 2021
Filed:
Apr 10, 2020
Appl. No.:
16/845259
Inventors:
- Armonk NY, US
Kirk D. PETERSON - Jericho VT, US
John B. DEFORGE - Barre VT, US
William V. HUOTT - Holmes NY, US
Uma SRINIVASAN - Poughkeepsie NY, US
Hyong Uk KIM - South Burlington VT, US
Michelle E. Finnefrock - Williston VT, US
Daniel RODKO - Poughkeepsie NY, US
International Classification:
G11C 29/00
Abstract:
A system may include an integrated circuit having repair select bits coupled with a central repair register. The repair register may be configured to determine how to broadcast multiple repair actions to a group of repairable circuits. Inclusion of the repair register may function to reduce the total number of latches used to hold repair information.

Optimizing Error Correcting Code In Three-Dimensional Stacked Memory

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US Patent:
20190220351, Jul 18, 2019
Filed:
Jan 16, 2018
Appl. No.:
15/872097
Inventors:
- ARMONK NY, US
DIYANESH B. CHINNAKKONDA VIDYAPOORNACHARY - BANGALORE, IN
SRIDHAR RANGARAJAN - BANGALORE, IN
KIRK D. PETERSON - JERICHO VT, US
JOHN B. DEFORGE - BARRE VT, US
International Classification:
G06F 11/10
G06F 3/06
G11C 29/52
G11C 5/02
G11C 5/06
Abstract:
Optimizing error correcting code (ECC) in three-dimensional (3D) stacked memory including selecting, as an ECC memory chip, a memory chip of a plurality of memory chips in a 3D stacked memory structure, wherein the 3D stacked memory structure comprises the plurality of memory chips stacked vertically and coupled together using through-silicon vias; determining that an error has been detected in one of the plurality of memory chips in the 3D stacked memory structure; selecting, based on the detected error, an order of an ECC decoder of the ECC stored in the ECC memory chip; and correcting the detected error in the 3D stacked memory structure using the ECC stored in the ECC memory chip.

Three-Dimensional Stacked Memory Optimizations For Latency And Power

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US Patent:
20190187915, Jun 20, 2019
Filed:
Dec 20, 2017
Appl. No.:
15/847954
Inventors:
- Armonk NY, US
John B. DeForge - Barre VT, US
Warren E. Maule - Cedar Park TX, US
Kirk D. Peterson - Jericho VT, US
Sridhar H. Rangarajan - Bangalore, IN
Saravanan Sethuraman - Bangalore, IN
International Classification:
G06F 3/06
G06F 9/455
G06F 13/42
Abstract:
An aspect includes receiving a request to write data to a memory that includes a stack of memory devices, each of the memory devices communicatively coupled to at least one other of the memory devices in the stack via a through silicon via (TSV). The write request is received by a hypervisor from an application executing on a virtual machine managed by the hypervisor. In response to receiving the request a latency requirement of accesses to the write data is determined. A physical location on a memory device in the stack of memory devices is assigned to the write data based at least in part on the latency requirement and a position of the memory device in the stack of memory devices. A write command that includes the physical location and the write data is sent to a memory controller.

Three-Dimensional Stacked Memory Access Optimization

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US Patent:
20190187930, Jun 20, 2019
Filed:
Dec 20, 2017
Appl. No.:
15/847957
Inventors:
- Armonk NY, US
John B. DeForge - Barre VT, US
Warren E. Maule - Cedar Park TX, US
Kirk D. Peterson - Jericho VT, US
Sridhar H. Rangarajan - Bangalore, IN
Saravanan Sethuraman - Bangalore, IN
International Classification:
G06F 3/06
G06F 13/16
G06F 11/10
G11C 29/52
G11C 11/409
G11C 5/06
G11C 5/02
Abstract:
An aspect includes receiving a request to access one or more memory devices in a stack of memory devices in a memory. Each of the memory devices are communicatively coupled to at least one other of the memory devices in the stack via a through silicon via (TSV). A current operating mode of the memory is determined in response to receiving the request. Based at least in part on the current operating mode of the memory being a first mode, a chip select switch is activated to provide access to exactly one of the memory devices in the stack of memory devices. Based at least in part on the current operating mode of the memory being a second mode, the chip select switch is activated to access all of the memory devices in the stack in parallel. The request is serviced using the activated chip select switch.
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John D Deforge from Barre, VTDeceased Get Report