Joe H Yu

20090106532, Apr 23, 2009

Mar 21, 2007

12/294223

Ata R. Khan - Saratoga CA, US
Rob Cosaro - San Jose CA, US
Joe Yu - Palo Alto CA, US

NXP B.V. - Eindhoven

G06F 15/76
G06F 9/02

712 36, 712E09002

Methods and apparatus suitable for rapid creation and configuration of microcontroller products, which include a microcontroller or similar computational resource, and configurable logic devices are described. Various embodiments of the present invention allow development of new microcontroller-based products and product families in a rapid and cost-effective manner, thereby enabling early entry of such products into the marketplace. An existing microcontroller block and existing configurable logic devices are combined to form a unique product, wherein the microcontroller block is operable to configure the configurable logic devices to form the desired unique hardware characteristics of the microcontroller-based product. The microcontroller block configures the configurable logic devices when the product is reset, and/or when a power-up condition is recognized.

55943667, Jan 14, 1997

Jun 19, 1995

8/492390

James C. K. Khong - San Jose CA
Wendey E. Mueller - Fremont CA
Joe Yu - Palo Alto CA
Neal Berger - Cupertino CA
Keith H. Gudger - Soquel CA
Geoffrey S. Gongwer - Campbell CA

Atmel Corporation - San Jose CA

H01L 2500
H03K 19177

326 41

A programmable logic device having a plurality of logic cells arranged in groups defining separate logic regions, both regional and multi-regional bus lines, and a crosspoint switch matrix which serves only to route signals from bus lines to inputs of the logic cells without logically combining two or more of the bus signals, i. e. without forming product terms. Rather, all logic is carried out by the logic cells themselves. In particular, the switch matrix is constructed so that each bus line can connect to one or more logic cell inputs, but each logic cell input can meaningfully connect to only one bus line without shorting. In one embodiment, each logic cell feeds one logic signal back to a regional bus line and can potentially feed back another logic signal through its region's universal select matrix to a universal bus line. The select matrix connects a subset of the region's potential feedback signals to the universal bus.

52313123, Jul 27, 1993

Mar 12, 1992

7/850285

Geoffrey S. Gongwer - San Jose CA
Jinglun Tam - Milpitas CA
Keith H. Gudger - Sunnyvale CA
Joe Yu - Palo Alto CA
Steven A. Sharp - Los Gatos CA

Atmel Corporation - San Jose CA

H03K 19177

307465

An integrated circuit package including a plurality of macrocells for connecting a logic circuit of the package to a plurality of external contacts of the package. At least one of the macrocells has an output driver that is enabled or disabled by a control signal for transmitting or preventing transmission of a logic signal to one of the contacts. The control signal is generated by a logic gate that receives and logically combines an individual output enable signal dedicated to that particular macrocell with a selected signal. One signal that may be selected is a regional output enable signal that is supplied to more than one macrocell. Each macrocell also has a feedback multiplexer selecting one signal to be sent to the logic circuit. Choices include a nonstored logic signal, a stored logic signal from a flip-flop register in the macrocell, a signal applied to the external contact associated with that macrocell, and a signal applied to another external contact associated with a different macrocell. A plurality of contacts are connected to feedback multiplexers in two different macrocells, and at least one contact connects in this manner to separate logic regions of the logic circuit.