Jing C Wu

20090322723, Dec 31, 2009

Jun 27, 2008

12/163685

Jing WU - San Diego CA, US

SONY CORPORATION - Tokyo
SONY ELECTRONICS INC. - Park Ridge NJ

G09G 5/00

345211

Method and apparatus for disabling use of a display device. In one embodiment, the method may include detecting a blackout timer setting for a display device, the blackout timer setting indicating a blackout period. The method may further include detecting a current time, determining if the current time lies within the blackout period indicated by the blackout timer, and disabling at least one function of the display device in response to the current time being within the blackout period.

20100011405, Jan 14, 2010

Jul 10, 2008

12/171077

Jing WU - San Diego CA, US

SONY CORPORATION - Tokyo
SONY ELECTRONICS INC. - Park Ridge NJ

H04N 7/173

725131

Method and apparatus for providing alternate audio data for a received broadcast media stream. In one embodiment, a method may include receiving a broadcast media stream including video data and audio data and detecting a channel setting of the receiving device, wherein the channel setting includes audio data associated with a channel of the broadcasted media stream. The method may further include detecting an audio setting associated with the channel of the broadcast media stream, wherein the audio setting corresponds to a user preferred audio data for the channel and outputting the video data and the audio data of the received broadcast media stream based, at least in part, on the user preferred audio data.

20210336760, Oct 28, 2021

Jul 9, 2021

17/305542

- San Diego CA, US
Jing WU - San Diego CA, US
Shih-Wei CHOU - San Diego CA, US

H04L 7/00

Methods, apparatus, and systems for communication over a multi-wire, multi-phase interface are disclosed. A clock recovery method includes generating a combination signal that includes transition pulses, each transition pulse being generated responsive to a transition in a difference signal representative of a difference in signaling state of a pair of wires in a three-wire bus. The combination signal is provided to a logic circuit that is configured to provide a clock signal as its output, where pulses in the combination signal cause the clock signal to be driven to a first state. The logic circuit receives a reset signal that is derived from the clock signal by delaying transitions to the first state while passing transitions from the first state without added delay. The clock signal is driven from the first state after passing a transition of the clock signal to the first state.

20210126765, Apr 29, 2021

Aug 25, 2020

17/001801

- San Diego CA, US
Jing WU - San Diego CA, US
Shih-Wei CHOU - San Diego CA, US

H04L 7/00

Methods, apparatus, and systems for communication over a multi-wire, multi-phase interface are disclosed. A clock recovery method includes generating a combination signal that includes transition pulses, each transition pulse being generated responsive to a transition in a difference signal representative of a difference in signaling state of a pair of wires in a three-wire bus. The combination signal is provided to a logic circuit that is configured to provide a clock signal as its output, where pulses in the combination signal cause the clock signal to be driven to a first state. The logic circuit receives a reset signal that is derived from the clock signal by delaying transitions to the first state while passing transitions from the first state without added delay. The clock signal is driven from the first state after passing a transition of the clock signal to the first state.

20190050958, Feb 14, 2019

Aug 14, 2018

16/103336

- San Diego CA, US
Pramod Vasant Argade - San Diego CA, US
Jing Wu - San Diego CA, US

G06T 1/20
G06F 9/38
G06T 5/00
G06F 9/30

A method for processing data in a graphics processing unit including receiving an indication that all threads of a warp in a graphics processing unit (GPU) are to execute a same branch in a first set of instructions, storing one or more predicate bits in a memory as a single set of predicate bits, wherein the single set of predicate bits applies to all of the threads in the warp, and executing a portion of the first set of instructions in accordance with the single set of predicate bits. Executing the first set of instructions may include executing the first set of instruction in accordance with the single set of predicate bits using a single instruction, multiple data (SIMD) processing core and/or executing the first set of instruction in accordance with the single set of predicate bits using a scalar processing unit.

20180165092, Jun 14, 2018

Dec 14, 2016

15/379195

- San Diego CA, US
Liang Han - San Diego CA, US
Lin Chen - San Diego CA, US
Chihong Zhang - San Diego CA, US
Hongjiang Shang - San Diego CA, US
Jing Wu - San Diego CA, US
Zilin Ying - San Diego CA, US
Chun Yu - Rancho Santa Fe CA, US
Guofang Jiao - San Diego CA, US
Andrew Gruber - Arlington MA, US
Eric Demers - San Diego CA, US

G06F 9/30
G06F 9/38

Systems and techniques are disclosed for general purpose register dynamic allocation based on latency associated with of instructions in processor threads. A streaming processor can include a general purpose registers configured to stored data associated with threads, and a thread scheduler configured to receive allocation information for the general purpose registers, the information describing general purpose registers that are to be assigned as persistent general purpose registers (pGPRs) and volatile general purpose registers (vGPRs). The plurality of general purpose registers can be allocated according to the received information. The streaming processor can include the general purpose registers allocated according to the received information, the allocated based on execution latencies of instructions included in the threads.

20180131503, May 10, 2018

Nov 10, 2016

15/348290

- San Diego CA, US
Yasser Ahmed - San Diego CA, US
Abhay Dixit - San Diego CA, US
Harry Huy Dang - San Diego CA, US
Jing Wu - San Diego CA, US

H04L 7/00
H04L 29/06

Methods, apparatus, and systems for data communication over a multi-wire, multi-phase interface are disclosed. A method for calibrating a clock recovery circuit includes recovering a first clock signal from transitions between pairs of symbols representative of successive signaling states of a 3-wire interface, where each pair of symbols includes a first symbol and a second symbol, generating a second clock signal by delaying the first clock signal by a first delay value, generating a third clock signal by delaying the second clock signal, calibrating the second clock signal and the third clock signal by initializing the first delay value such that the first sampling circuit, the second sampling circuit and the third sampling circuit capture the same symbol in a first pair of symbols, and incrementally increasing the first delay value until the second sampling circuit and the third sampling circuit capture different symbols from each pair of symbols.

20180062883, Mar 1, 2018

Aug 18, 2017

15/680959

- San Diego CA, US
Abhay Dixit - San Diego CA, US
Shih-Wei Chou - San Diego CA, US
Jing Wu - San Diego CA, US
Harry Dang - San Diego CA, US

H04L 25/02
H04B 3/462
H03K 5/135
H04L 7/00
H04L 25/14
H04L 25/49
G01R 31/317

Methods, apparatus, and systems for data communication over a multi-wire, multi-phase interface are disclosed. A method of calibration includes configuring a 3-phase signal to include a high frequency component and a low frequency component during a calibration period, and transmitting a version of the 3-phase signal on each wire of a 3-wire interface. The version of the 3-phase signal transmitted on each wire is out-of-phase with the versions of the 3-phase signal transmitted on each of the other wires of the 3-wire interface. The 3-phase signal may be configured to enable a receiver to determine certain operating parameters of the 3-wire interface.