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Jin Lin Phones & Addresses

  • Castro Valley, CA

Professional Records

Lawyers & Attorneys

Jin Lin Photo 1

Jin Lin - Lawyer

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ISLN:
1000229592
Admitted:
2016

Resumes

Resumes

Jin Lin Photo 2

Jin Lin

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Work:
UCT Manufacturing
South San Francisco, CA
Jul 2009 to Jul 2012
CNC Mill Setup Machinist

Quattro MFG. Union City

1997 to 2005

Long's MFG
Fremont, CA
1994 to 1996
CNC mill operator in Long's MFG. Fremont city

Business Records

Name / Title
Company / Classification
Phones & Addresses
Jin Zhao Lin
President
Good Year Trading Inc
2 Willet Ct, Alameda, CA 94501
Jin Zhao Lin
Principal
Lin, Jin Zhao
Business Services at Non-Commercial Site
2 Willet Ct, Alameda, CA 94501
Jin Lin
SPRING PROPERTY MANAGEMENT LLC
Jin Lin
Y&W INTERNATIONAL LLC
Jin Kui Lin
NEW CITY INTERNATIONAL BUFFET, INC
Jin He Lin
LIN CHEN INC
Jin Lin
GREENSVIEW APARTMENTS, LLC
Jin Lin
H Y & W LLC

Publications

Us Patents

Method And System For Array Optimization

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US Patent:
8122442, Feb 21, 2012
Filed:
Jan 31, 2008
Appl. No.:
12/023061
Inventors:
Jin Lin - San Jose CA, US
Assignee:
Oracle America, Inc. - Redwood City CA
International Classification:
G06F 9/44
G06F 9/45
US Classification:
717159, 717149, 717151
Abstract:
A method for transforming access to a structure array, that includes compiling source code, wherein compiling the source code includes identifying the structure array in the source code, performing an object safety analysis to determine whether the structure array is safe for transformation, wherein the object safety analysis includes an inter-procedural alias class analysis, performing a profitability analysis on the structure array when the structure array is safe for transformation, wherein the profitability analysis includes selecting a transformation from a plurality of transformations, wherein the plurality of transformations includes a pointer based fully splitting transformation, a pointer based partially splitting transformation, and an address based fully splitting transformation, and performing the selected transformation on the structure array, and storing the compiled code.

Aggressive Loop Parallelization Using Speculative Execution Mechanisms

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US Patent:
8291197, Oct 16, 2012
Filed:
Feb 12, 2007
Appl. No.:
11/673905
Inventors:
Yuguang Wu - Mountain View CA, US
Jin Lin - San Jose CA, US
Assignee:
Oracle America, Inc. - Redwood City CA
International Classification:
G06F 15/00
G06F 9/30
G06F 9/40
US Classification:
712216
Abstract:
A system and method for aggressive loop parallelization using speculative execution is disclosed. The method may include transforming code of a target application for concurrent execution, which may include adding an instruction to create a global address table entry for each store operation on which a load operation of a different loop iteration is dependent. The method may include replacing a standard load instruction with a special instruction configured to determine if an operand address of the load matches an operand address in one of the global address table entries. Another special instruction may remove a table entry following execution of the corresponding store operation. If an operand address of a load of a currently executing thread matches an operand address in the global address table, the method may include setting a checkpoint, completing execution of the thread in a pre-fetch mode, and re-executing the thread from the checkpoint.

Adjustable Hip-End Purlin

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US Patent:
8443568, May 21, 2013
Filed:
Dec 23, 2010
Appl. No.:
12/978374
Inventors:
Jin Jie Lin - Livermore CA, US
Assignee:
Simpson Strong-Tie Company, Inc. - Pleasanton CA
International Classification:
E04C 3/02
US Classification:
52690, 52686, 526551
Abstract:
A structural connection between the upper outer edges of multiple structural members with one or more elongate connectors that span from edge to edge between pairs of structural members.

Speculative Region-Level Loop Optimizations

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US Patent:
8589901, Nov 19, 2013
Filed:
Dec 22, 2010
Appl. No.:
12/976463
Inventors:
Jin Lin - San Jose CA, US
John L. Ng - San Jose CA, US
Robert J. Cox - Mountain View CA, US
Xinmin Tian - Union City CA, US
International Classification:
G06F 9/45
US Classification:
717160
Abstract:
A system and method are configured to apply region level optimizations to a selected region of source code rather than loop level optimizations to a loop or loop nest. The region may include an outer loop, a plurality of inner loops and at least one control code. If the region includes an exceptional control flow statement and/or a procedure call, speculative region-level multi-versioning may be applied.

Speculative Compilation To Generate Advice Messages

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US Patent:
20120117552, May 10, 2012
Filed:
Nov 9, 2010
Appl. No.:
12/942543
Inventors:
Rakesh Krishnaiyer - Milpitas CA, US
Hideki Saito Ido - Sunnyvale CA, US
Ernesto Su - Campbell CA, US
John L. Ng - San Jose CA, US
Jin Lin - San Jose CA, US
Xinmin Tian - Union City CA, US
Robert Y. Geva - Cupertino CA, US
International Classification:
G06F 9/45
US Classification:
717160, 717159
Abstract:
Methods to improve optimization of compilation are presented. In one embodiment, a method includes identifying one or more optimization speculations with respect to a code region and speculatively performing transformation on an intermediate representation of the code region in accordance with an optimization speculation. The method includes generating an advice message corresponding to the optimization speculation and displaying the advice message if the optimization speculation results in an improved compilation result.

Loop Parallelization Based On Loop Splitting Or Index Array

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US Patent:
20120167069, Jun 28, 2012
Filed:
Dec 24, 2010
Appl. No.:
12/978465
Inventors:
Jin Lin - San Jose CA, US
Nishkam Ravi - Princeton NJ, US
Xinmin Tian - Union City CA, US
John L. Ng - San Jose CA, US
Renat V. Valiullin - Novosibirsk, RU
International Classification:
G06F 9/45
US Classification:
717160
Abstract:
Methods and apparatus to provide loop parallelization based on loop splitting and/or index array are described. In one embodiment, one or more split loops, corresponding to an original loop, are generated based on the mis-speculation information. In another embodiment, a plurality of subloops are generated from an original loop based on an index array. Other embodiments are also described.

Techniques For Displaying Secure Content For An Application Through User Interface Context File Switching

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US Patent:
20180336325, Nov 22, 2018
Filed:
May 15, 2018
Appl. No.:
15/980698
Inventors:
- Cupertino CA, US
Jin Bing LIN - Mountain View CA, US
Stephen F. HOLT - San Francisco CA, US
David A. SCHAEFGEN - San Jose CA, US
Nils M. HAYAT - San Francisco CA, US
Jeffrey Y. HAYASHIDA - San Francisco CA, US
International Classification:
G06F 21/31
Abstract:
Disclosed herein is a technique that can selectively display secure content on a computing device. The technique can detect both lock and unlock events and issue appropriate control signals that cause an application to display a more secure version of the application when necessary based on a particular UI context file. The UI context file can specify a configuration that includes pre-configured hidden or removed UI elements that do not need to be adjusted at runtime. Moreover, the technique can seamlessly pivot to a different UI context file that specifies a configuration of the application that allows the user to experience the full-capabilities of the application when the computing device is in an unlocked-mode.
Jin T Lin from Castro Valley, CA Get Report