Jim J Park from 7032 Ledgefern Cir, San Ramon, CA 94582, age 58

Interconnection And Input/Output Resources For Programmable Logic Integrated Circuit Devices

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US Patent:

6407576, Jun 18, 2002

Filed:

Mar 2, 2000

Appl. No.:

09/516921

Inventors:

Tony Ngai - Campbell CA
Bruce Pedersen - San Jose CA
James Schleicher - Santa Clara CA
Wei-Jen Huang - Burlingame CA
Michael Hutton - Palo Alto CA
Victor Maruri - Mountain View CA
Rakesh Patel - Cupertino CA
Peter J. Kazarian - Cupertino CA
Andrew Leaver - Palo Alto CA
David W. Mendel - Sunnyvale CA
Jim Park - San Jose CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

H01L 2500

US Classification:

326 41, 326 39, 326 47

Abstract:

A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e. g. , interconnection conductors, signal buffers/drivers, programmable connectors, etc. ) are provided on the device for making programmable interconnections to, from, and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e. g. , with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources may have what may be termed normal signal speed, while a smaller minor portion may have significantly faster signal speed. Secondary (e. g. , clock and clear) signal distribution may also be enhanced, and so may be input/output circuitry and cascade connections between adjacent or nearby logic modules on the device.

Interconnection And Input/Output Resources For Programmable Logic Integrated Circuit Devices

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US Patent:

6894533, May 17, 2005

Filed:

Jun 9, 2003

Appl. No.:

10/458431

Inventors:

Tony Ngai - Campbell CA, US
Bruce Pedersen - San Jose CA, US
James Schleicher - Santa Clara CA, US
Wei-Jen Huang - Burlingame CA, US
Michael Hutton - Palo Alto CA, US
Victor Maruri - Mountain View CA, US
Rakesh Patel - Cupertino CA, US
Peter J. Kazarian - Cupertino CA, US
Andrew Leaver - Palo Alto CA, US
David W. Mendel - Sunnyvale CA, US
Jim Park - San Jose CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03K019/177

US Classification:

326 41, 326 39, 326 40

Abstract:

A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e. g. , interconnection conductors, signal buffers/drivers, programmable connectors, etc. ) are provided on the device for making programmable interconnections to, from, and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e. g. , with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources may have what may be termed normal signal speed, while a smaller minor portion may have significantly faster signal speed. Secondary (e. g. , clock and clear) signal distribution may also be enhanced, and so may be input/output circuitry and cascade connections between adjacent or nearby logic modules on the device.

Flexible Macrocell Interconnect

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US Patent:

6927601, Aug 9, 2005

Filed:

Nov 21, 2002

Appl. No.:

10/301506

Inventors:

Guu Lin - San Jose CA, US
Stephanie Tran - San Jose CA, US
Bruce Pederson - San Jose CA, US
Brad Vest - San Jose CA, US
Jim Park - San Jose CA, US
Jay Schleicher - Santa Clara CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03K019/177

US Classification:

326 41, 326 47

Abstract:

Methods and apparatus for novel routing structures and methods that improve fitting of user-defined functions onto programmable logic devices. In particular, second time fitting is improved. Exemplary structures and methods include allowing product terms to be expanded using inputs from more than one neighboring macrocell by providing multiple expansion and bypassing paths. Also, product term OR shifting prevents macrocell output stages from being buried and made inaccessible, and macrocell outputs are provided on expander word lines, increasing efficiency of those lines, as well as conserving routing resources. Expansion, bypassing, OR shifting, and expander word lines may terminate at logic array block boundaries or may continue beyond these boundaries to other logic array blocks.

Interconnection And Input/Output Resources For Programmable Logic Integrated Circuit Devices

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US Patent:

6989689, Jan 24, 2006

Filed:

May 24, 2004

Appl. No.:

10/852858

Inventors:

Tony Ngai - Campbell CA, US
Bruce Pedersen - San Jose CA, US
James Schleicher - Santa Clara CA, US
Wei-Jen Huang - Burlingame CA, US
Michael Hutton - Palo Alto CA, US
Victor Maruri - Mountain View CA, US
Rakesh Patel - Cupertino CA, US
Peter J. Kazarian - Cupertino CA, US
Andrew Leaver - Palo Alto CA, US
David W. Mendel - Sunnyvale CA, US
Jim Park - San Jose CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03K 19/177

US Classification:

326 41, 326 39, 326 47

Abstract:

A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e. g. , interconnection conductors, signal buffers/drivers, programmable connectors, etc. ) are provided on the device for making programmable interconnections to, from, and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e. g. , with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources may have what may be termed normal signal speed, while a smaller minor portion may have significantly faster signal speed. Secondary (e. g. , clock and clear) signal distribution may also be enhanced, and so may be input/output circuitry and cascade connections between adjacent or nearby logic modules on the device.

Interconnection Resources For Programmable Logic Integrated Circuit Devices

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US Patent:

7123052, Oct 17, 2006

Filed:

Mar 22, 2005

Appl. No.:

11/087377

Inventors:

James Schleicher - Santa Clara CA, US
Jim Park - San Jose CA, US
Bruce Pederson - San Jose CA, US
Tony Ngai - Campbell CA, US
Wei-Jen Huang - Burlingame CA, US
Victor Maruri - Mountain View CA, US
Rakesh Patel - Cupertino CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03K 19/177

US Classification:

326 41, 326 39

Abstract:

A programmable logic device has many regions of programmable logic, together with relatively general-purpose, programmable, interconnection resources that can be used to make interconnections between virtually any of the logic regions. In addition, various types of more local interconnection resources are associated with each logic region for facilitating the making of interconnections between adjacent or nearby logic regions without the need to use the general-purpose interconnection resources for those interconnections. The local interconnection resources support flexible clustering of logic regions via relatively direct and therefore high-speed interconnections, preferably in both horizontal and vertical directions in the typically two-dimensional array of logic regions. The logic region clustering options provided by the local interconnection resources are preferably boundary-less or substantially boundary-less within the array of logic regions.

Flexible Macrocell Interconnect

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US Patent:

7161384, Jan 9, 2007

Filed:

Jul 12, 2005

Appl. No.:

11/180069

Inventors:

Guu Lin - San Jose CA, US
Stephanie Tran - San Jose CA, US
Bruce Pederson - San Jose CA, US
Brad Vest - San Jose CA, US
Jim Park - San Jose CA, US
Jay Schleicher - Santa Clara CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03K 19/177

US Classification:

326 41, 326 47

Abstract:

Methods and apparatus for novel routing structures and methods that improve fitting of user-defined functions onto programmable logic devices. In particular, second time fitting is improved. Exemplary structures and methods include allowing product terms to be expanded using inputs from more than one neighboring macrocell by providing multiple expansion and bypassing paths. Also, product term OR shifting prevents macrocell output stages from being buried and made inaccessible, and macrocell outputs are provided on expander word lines, increasing efficiency of those lines, as well as conserving routing resources. Expansion, bypassing, OR shifting, and expander word lines may terminate at logic array block boundaries or may continue beyond these boundaries to other logic array blocks.

Method And Apparatus For Comparing And Synchronizing Programmable Logic Device User Configuration Dataset Versions

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US Patent:

7277902, Oct 2, 2007

Filed:

Apr 18, 2005

Appl. No.:

11/108370

Inventors:

Jim Park - San Jose CA, US
Mihail Iotov - San Jose CA, US
Michael V. Wenzler - Oakland CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

G06F 12/00

US Classification:

707203, 707205, 716 17

Abstract:

A graphical tool assists a user in migrating programming changes from one programmable logic device to another. The tool preferably compares a new user configuration dataset (e. g. , the user configuration dataset including old features as well as newly-added features) for the “origin” programmable logic device to the existing user configuration dataset (i. e. , the user configuration dataset including only old features) for a “destination” programmable logic device, and displays differences to the user. The tool preferably also assists the user to synchronize the devices by “copying” the new features of the user configuration dataset for one device into the old user configuration dataset for another device to the extent possible, by providing graphical inputs to allow the user to indicate which features should be synchronized, or to graphically manipulate the feature assignments directly.

Interconnection And Input/Output Resources For Programmable Logic Integrated Circuit Devices

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US Patent:

7492188, Feb 17, 2009

Filed:

Jul 30, 2007

Appl. No.:

11/888317

Inventors:

Tony Ngai - Campbell CA, US
Bruce Pedersen - San Jose CA, US
James Schleicher - Santa Clara CA, US
Wei-Jen Huang - Burlingame CA, US
Michael Hutton - Palo Alto CA, US
Victor Maruri - Mountain View CA, US
Rakesh Patel - Cupertino CA, US
Peter J. Kazarian - Cupertino CA, US
Andrew Leaver - Palo Alto CA, US
David W. Mendel - Sunnyvale CA, US
Jim Park - San Jose CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

H01L 25/00
H03K 19/177

US Classification:

326 41, 326 37, 326 47

Abstract:

A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e. g. , interconnection conductors, signal buffers/drivers, programmable connectors, etc. ) are provided on the device for making programmable interconnections to, from, and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e. g. , with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources may have what may be termed normal signal speed, while a smaller minor portion may have significantly faster signal speed. Secondary (e. g. , clock and clear) signal distribution may also be enhanced, and so may be input/output circuitry and cascade connections between adjacent or nearby logic modules on the device.