Jenny S Hu

20120289236, Nov 15, 2012

Aug 25, 2011

13/217743

LIMEI XU - MOUNTAIN VIEW CA, US
JENNY HU - CUPERTINO CA, US

H04W 40/00

455446

This invention relates to a method for controlling location distribution of sensing nodes, selection of sensing nodes, control of sensing implementation and process of performing spectrum sensing in cognitive radio networks of open wireless architecture (OWA) systems. Specifically, the invention relates to an efficient and reliable method minimizing time overhead consumed during spectrum sensing with open wireless architecture (OWA).

20230077843, Mar 16, 2023

Aug 12, 2022

17/887222

- Cupertino CA, US
Mehmet N Agaoglu - Dublin CA, US
Gokhan Avkarogullari - San Jose CA, US
Jenny Hu - Sunnyvale CA, US
Alexander K Kan - San Carlos CA, US
Yuhui Li - Cupertino CA, US
James R Montgomerie - Sunnyvale CA, US
Andrey Pokrovskiy - Mountain View CA, US
Yingying Tang - Cupertino CA, US
Chaohao Wang - Shanghai, CN

G09G 5/36

An electronic device may include a display. Control circuitry may operate the display at different frame rates such as 60 Hz, 80 Hz, and 120 Hz. The control circuitry may determine which frame rate to use based on a speed of animation on the display and based on a type of animation on the display. To mitigate the appearance of judder as the display frame rate changes, the control circuitry may implement techniques such as hysteresis (e.g., windows of tolerance around speed thresholds to ensure that the display frame rate does not change too frequently as a result of noise), speed thresholds that are based on a user perception study, consistent latency between touch input detection and corresponding display output across different frame rates (e.g., using a fixed touch scan rate that is independent of frame duration), and animation-specific speed thresholds for triggering frame rate changes.

20210043754, Feb 11, 2021

Oct 26, 2020

17/080713

- Santa Clara CA, US
Jenny HU - Santa Clara CA, US
Anindya DASGUPTA - Portland OR, US
Michael L. HATTENDORF - Portland OR, US
Christopher P. AUTH - Portland OR, US

H01L 29/66
H01L 29/78
H01L 21/285
H01L 21/02
H01L 27/088
H01L 29/06
H01L 21/8234
H01L 21/768
H01L 21/8238
H01L 29/417
H01L 21/311
H01L 27/092
H01L 29/08
H01L 21/762
H01L 21/033
H01L 21/28
H01L 21/308
H01L 49/02
H01L 23/532
H01L 27/02
H01L 23/528
H01L 29/167
H01L 23/522
H01L 29/165
H01L 27/11
H01L 29/51
H01L 23/00

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a semiconductor substrate comprising an N well region having a semiconductor fin protruding therefrom. A trench isolation layer is on the semiconductor substrate around the semiconductor fin, wherein the semiconductor fin extends above the trench isolation layer. A gate dielectric layer is over the semiconductor fin. A conductive layer is over the gate dielectric layer over the semiconductor fin, the conductive layer comprising titanium, nitrogen and oxygen. A P-type metal gate layer is over the conductive layer over the semiconductor fin.

20200388213, Dec 10, 2020

Apr 17, 2020

16/852339

- Cupertino CA, US
Xiaokai Li - Mountain View CA, US
Shawn Hurley - Sunnyvale CA, US
Adria Fores Herranz - Barcelona, ES
Yingying Tang - Mountain View CA, US
Jenny Hu - Santa Clara CA, US
Koorosh Aflatooni - Los Altos Hills CA, US
Chaohao Wang - Sunnyvale CA, US

G09G 3/3225

A flat-panel display device and method to unify response times for all possible grey level transitions in a flat-panel display or an augmented reality display. A pixel drive compensator receives a frame from a graphics processing unit and two-dimensional temperature for pixels at a display panel to compensate for temperature variation across the display panel.

20200335603, Oct 22, 2020

Jul 1, 2020

16/918816

- Santa Clara CA, US
Jenny HU - Santa Clara CA, US
Anindya DASGUPTA - Portland OR, US
Michael L. HATTENDORF - Portland OR, US
Christopher P. AUTH - Portland OR, US

H01L 29/66
H01L 29/78
H01L 27/088
H01L 21/762
H01L 29/06
H01L 21/8234
H01L 21/768
H01L 23/522
H01L 23/532
H01L 29/165
H01L 29/417
H01L 21/033
H01L 21/28
H01L 21/285
H01L 21/308
H01L 21/311
H01L 21/8238
H01L 23/528
H01L 27/092
H01L 27/11
H01L 49/02
H01L 29/08
H01L 29/51
H01L 27/02
H01L 21/02
H01L 29/167

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. A gate dielectric layer is over a top of the fin and laterally adjacent sidewalls of the fin. An N-type gate electrode is over the gate dielectric layer over the top of the fin and laterally adjacent the sidewalls of the fin, the N-type gate electrode comprising a P-type metal layer on the gate dielectric layer, and an N-type metal layer on the P-type metal layer. A first N-type source or drain region is adjacent a first side of the gate electrode. A second N-type source or drain region is adjacent a second side of the gate electrode, the second side opposite the first side.

20200321449, Oct 8, 2020

Jun 22, 2020

16/908468

- Santa Clara CA, US
Jenny HU - Santa Clara CA, US
Anindya DASGUPTA - Portland OR, US
Michael L. HATTENDORF - Portland OR, US
Christopher P. AUTH - Portland OR, US

H01L 29/66
H01L 29/78
H01L 27/088
H01L 21/762
H01L 29/06
H01L 21/8234
H01L 21/768
H01L 23/522
H01L 23/532
H01L 29/165
H01L 29/417
H01L 21/033
H01L 21/28
H01L 21/285
H01L 21/308
H01L 21/311
H01L 21/8238
H01L 23/528
H01L 27/092
H01L 27/11
H01L 49/02
H01L 29/08
H01L 29/51
H01L 27/02
H01L 21/02
H01L 29/167

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a semiconductor substrate comprising an N well region having a semiconductor fin protruding therefrom. A trench isolation layer is on the semiconductor substrate around the semiconductor fin, wherein the semiconductor fin extends above the trench isolation layer. A gate dielectric layer is over the semiconductor fin. A conductive layer is over the gate dielectric layer over the semiconductor fin, the conductive layer comprising titanium, nitrogen and oxygen. A P-type metal gate layer is over the conductive layer over the semiconductor fin.

20190164968, May 30, 2019

Dec 30, 2017

15/859355

- Santa Clara CA, US
Jenny HU - Santa Clara CA, US
Anindya DASGUPTA - Portland OR, US
Michael L. HATTENDORF - Portland OR, US
Christopher P. AUTH - Portland OR, US

H01L 27/092
H01L 29/78
H01L 21/762
H01L 21/8234
H01L 21/8238
H01L 21/311
H01L 29/08
H01L 27/11
H01L 29/66
H01L 21/308
H01L 27/088
H01L 29/51
H01L 21/285
H01L 21/28
H01L 21/033
H01L 21/768
H01L 23/532
H01L 23/522
H01L 23/528
H01L 49/02

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. A gate dielectric layer is over a top of the fin and laterally adjacent sidewalls of the fin. An N-type gate electrode is over the gate dielectric layer over the top of the fin and laterally adjacent the sidewalls of the fin, the N-type gate electrode comprising a P-type metal layer on the gate dielectric layer, and an N-type metal layer on the P-type metal layer. A first N-type source or drain region is adjacent a first side of the gate electrode. A second N-type source or drain region is adjacent a second side of the gate electrode, the second side opposite the first side.

20190164969, May 30, 2019

Dec 30, 2017

15/859356

- Santa Clara CA, US
Jenny HU - Santa Clara CA, US
Anindya DASGUPTA - Portland OR, US
Michael L. HATTENDORF - Portland OR, US
Christopher P. AUTH - Portland OR, US

H01L 27/092
H01L 29/66
H01L 21/762
H01L 21/8238
H01L 29/06
H01L 29/78

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a semiconductor substrate comprising an N well region having a semiconductor fin protruding therefrom. A trench isolation layer is on the semiconductor substrate around the semiconductor fin, wherein the semiconductor fin extends above the trench isolation layer. A gate dielectric layer is over the semiconductor fin. A conductive layer is over the gate dielectric layer over the semiconductor fin, the conductive layer comprising titanium, nitrogen and oxygen. A P-type metal gate layer is over the conductive layer over the semiconductor fin.