Jay Song Chun

20090023293, Jan 22, 2009

Jul 19, 2007

11/780079

Jay S. Chun - Plano TX, US

H01L 21/461
G01B 21/22

438707, 702 85, 257E21483

In accordance with the invention, there are methods of controlling the sidewall angle of a polysilicon gate from batch to batch while maintaining current bottom critical dimension control performance. The method can include generating a correlation between a sidewall angle of a gate and RF bias power and etch time of one or more etch steps during the formation of the gate, developing a statistical model for the sidewall angle as a function of one or more of polysilicon density, polythickness, and etcher, and predicting a sidewall angle using the statistical model for a given polydensity, a given polythickness, and a given etcher. The method can also include comparing the predicted sidewall angle with a target sidewall angle and determining an optimized RF bias power and optimized etch time of one or more etch steps during the formation of the gate using the correlation to match the target sidewall angle.

20210143249, May 13, 2021

Jan 25, 2021

17/156793

- Dallas TX, US
JEFFREY A. WEST - DALLAS TX, US
THOMAS D. BONIFIELD - DALLAS TX, US
JOSEPH ANDRE GALLEGOS - DALLAS TX, US
JAY SUNG CHUN - PLANO TX, US
ZHIYI YU - ALLEN TX, US

H01L 49/02

An integrated capacitor on a semiconductor surface on a substrate includes a capacitor dielectric layer including at least one silicon compound material layer on a bottom plate. The capacitor dielectric layer includes a pitted sloped dielectric sidewall. Each of the pits is at least partially filled by one of a plurality of noncontiguous dielectric portions. A conformal dielectric layer may be formed over the noncontiguous dielectric portions. A top metal layer provides a top plate of the capacitor.

20190198604, Jun 27, 2019

Dec 21, 2017

15/850999

- Dallas TX, US
Jeffrey Alan West - Dallas TX, US
Thomas D. Bonifield - Dallas TX, US
Jay Sung Chun - Plano TX, US
Byron Lovell Williams - Plano TX, US

H01L 49/02
H01L 21/027
H01L 21/311
H01L 21/02
H01L 23/522

Methods of fabricating a thick oxide feature on a semiconductor wafer include forming a oxide layer having a thickness of at least six micrometers and depositing a photoresist layer on the oxide layer. The oxide layer has a first etch rate of X with a given etchant, the photoresist layer has a second etch rate of Y with the given etchant and the ratio of X:Y is less than 4:1. Prior to etching the photoresist layer and the oxide layer, the photoresist layer is patterned with a grayscale mask that creates a photoresist layer having a sidewall that forms an angle with the horizontal that is less than or equal to 10 degrees.

20180130870, May 10, 2018

Nov 10, 2016

15/348580

- Dallas TX, US
JEFFREY A. WEST - DALLAS TX, US
THOMAS D. BONIFIELD - DALLAS TX, US
JOSEPH ANDRE GALLEGOS - DALLAS TX, US
JAY SUNG CHUN - PLANO TX, US
ZHIYI YU - ALLEN TX, US

H01L 49/02
H01L 21/02
H01L 21/311

A method of forming an integrated capacitor on a semiconductor surface on a substrate includes etching a capacitor dielectric layer including at least one silicon compound material layer on a bottom plate which is above and electrically isolated from the semiconductor surface to provide at least one defined dielectric feature having sloped dielectric sidewall portion. A dielectric layer is deposited to at least partially fill pits in the sloped dielectric sidewall portion to smooth a surface of the sloped dielectric sidewall portion. The dielectric layer is etched, and a top plate is then formed on top of the dielectric feature.