Man Tang Phones & Addresses
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San Jose, CA
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Sunnyvale, CA
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Cupertino, CA
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Pleasant Hill, CA
Work
Company:
Babcock and brown
Address:
2 Harrison St Fl 6, San Francisco, CA 94105
Phones:
(415) 512-1515
Position:
Chairman
Industries:
Industrial Organic Chemicals
Business Records
Name / Title
Company / Classification
Phones & Addresses
Chairman
Babcock and Brown
Industrial Organic Chemicals
Industrial Organic Chemicals
2 Harrison St Fl 6, San Francisco, CA 94105
Chairman Of The Board
T. Y. Lin International
Business Services
Business Services
2 Harrison St Ste 500, Santa Clara, CA 95054
Chairman Of The Board
T. Y. Lin International
2 Harrison St STE 500, Santa Clara, CA 95054
(408) 765-8080
(408) 765-8080
SUN HING, INC
Chairman
Babcock and Brown
Industrial Organic Chemicals
Industrial Organic Chemicals
2 Harrison St Fl 6, San Francisco, CA 94105
Chairman Of The Board
T. Y. Lin International
Business Services
Business Services
2 Harrison St Ste 500, Santa Clara, CA 95054
Publications
Us Patents
Memory Processing System And Method For Accessing Memory Including Reordering Memory Requests To Reduce Mode Switching
View pageUS Patent:
6564304, May 13, 2003
Filed:
Sep 1, 2000
Appl. No.:
09/653763
Inventors:
Timothy J. Van Hook - Atherton CA
Man Kit Tang - Saratoga CA
Man Kit Tang - Saratoga CA
Assignee:
ATI Technologies Inc. - Ontario
International Classification:
G06F 1314
US Classification:
711154, 711157, 711158, 710 39, 345535
Abstract:
A memory processing system and method for accessing memory in a graphics processing system are disclosed in which memory accesses are reordered. A memory controller arbitrates memory access requests from a plurality of memory requesters (referred to as âmastersâ). Reads are grouped together and writes are grouped together to avoid mode switching. Instructions are reordered to minimize page switches. In one embodiment, reads are given priority and writes are deferred. The memory accesses come from different masters. Each master provides memory access requests into its own associated request queue. The master provides page break decisions and other optimization information in its own queue. The masters also notify the memory controller of their latency requirements. The memory controller uses the queue and page break decisions to reorder the requests from all queues for efficient page and bank access while considering latency requirements.
Programmable Partitionable Counter
View pageUS Patent:
20130332708, Dec 12, 2013
Filed:
Jun 6, 2013
Appl. No.:
13/912033
Inventors:
Jay Patel - Los Gatos CA, US
Man Kit Tang - Saratoga CA, US
Man Kit Tang - Saratoga CA, US
International Classification:
G06F 9/30
US Classification:
712225
Abstract:
An integrated circuit device for receiving packets. The integrated circuit device includes a programmable partitionable counter that includes a first counter partition for counting a number of the packets, and a second counter partition for counting bytes of the packets. The first counter partition and the second counter partition are configured to be incremented by a single command from the packet processor.
Conflict Resolution In Interleaved Memory Systems With Multiple Parallel Accesses
View pageUS Patent:
57404020, Apr 14, 1998
Filed:
Jun 13, 1995
Appl. No.:
8/487240
Inventors:
Joseph P. Bratt - San Jose CA
John Brennen - Mountain View CA
Peter Y. Hsu - Fremont CA
Joseph T. Scanlon - Sunnyvale CA
Man Kit Tang - Milpitas CA
Steven J. Ciavaglia - Willinston VT
John Brennen - Mountain View CA
Peter Y. Hsu - Fremont CA
Joseph T. Scanlon - Sunnyvale CA
Man Kit Tang - Milpitas CA
Steven J. Ciavaglia - Willinston VT
Assignee:
Silicon Graphics, Inc. - Mountain View CA
International Classification:
G06F 1200
US Classification:
395484
Abstract:
A conflict resolution system for interleaved memories in processors capable of issuing multiple independent memory operations per cycle. The conflict resolution system includes an address bellow for temporarily storing memory requests, and cross-connect switches to variously route multiple parallel memory requests to multiple memory banks. A control logic block controls the address bellow and the cross-connect switches to reorder the sequence of memory requests to avoid conflicts. The reordering removes conflicts and increases the occurrence of alternating memory requests that can issue simultaneously.
Debug Mode For A Superscalar Risc Processor
View pageUS Patent:
55375383, Jul 16, 1996
Filed:
Dec 15, 1993
Appl. No.:
8/166969
Inventors:
Joseph P. Bratt - San Jose CA
John Brennan - Mountain View CA
Peter Y. Hsu - Fremont CA
Chandra S. Joshi - Saratoga CA
William A. Huffman - Los Gatos CA
Monica R. Nofal - Los Altos CA
Paul Rodman - Palo Alto CA
Joseph T. Scanlon - Sunnyvale CA
Man K. Tang - Milpitas CA
John Brennan - Mountain View CA
Peter Y. Hsu - Fremont CA
Chandra S. Joshi - Saratoga CA
William A. Huffman - Los Gatos CA
Monica R. Nofal - Los Altos CA
Paul Rodman - Palo Alto CA
Joseph T. Scanlon - Sunnyvale CA
Man K. Tang - Milpitas CA
Assignee:
Silicon Graphics, Inc. - Mountain View CA
International Classification:
G06F 1134
G06F 930
G06F 930
US Classification:
39518314
Abstract:
A processor system that is switchable between a normal mode of operation without precise floating point exceptions and a debug mode of operation with precise floating point exceptions. The processor system includes a dispatch for dispatching integer and floating point instructions, an integer unit having a multi-stage integer pipeline for executing the integer instructions, and a floating point unit having a multi-stage floating point pipeline for executing the floating point instructions. The system begins operation in the normal mode, and upon receipt of an instruction to "switch to debug mode," the processor switches to the debug mode of operation with precise exceptions. In the debug mode, once a floating point instruction has been dispatched, all other instructions are prevented from being committed until the system determines whether the floating point instruction generates an exception. Thus, permitting the system to signal precise exceptions when not in the normal mode.
Memory System Including Local And Global Caches For Storing Floating Point And Integer Data
View pageUS Patent:
55109349, Apr 23, 1996
Filed:
Dec 15, 1993
Appl. No.:
8/168832
Inventors:
John Brennan - Mountain View CA
Peter Y. Hsu - Fremont CA
William A. Huffman - Los Gatos CA
Paul Rodman - Palo Alto CA
Joseph T. Scanlon - Sunnyvale CA
Man K. Tang - Milpitas CA
Steve J. Ciavaglia - Williston VT
Peter Y. Hsu - Fremont CA
William A. Huffman - Los Gatos CA
Paul Rodman - Palo Alto CA
Joseph T. Scanlon - Sunnyvale CA
Man K. Tang - Milpitas CA
Steve J. Ciavaglia - Williston VT
Assignee:
Silicon Graphics, Inc. - Mountain View CA
International Classification:
G06F 1200
G06F 1300
G06F 1300
US Classification:
395446
Abstract:
A split level cache memory system for a data processor includes a single chip integer unit, an army processor such as a floating point unit, an external main memory and a split level cache. The split level cache includes an on-chip, fast local cache with low latency for use by the integer unit for loads and stores of integer and address data and an off-chip, pipelined global cache for storing arrays of data such as floating point data for use by the array processor and integer and address data for refilling the local cache. Coherence between the local cache and global cache is maintained by writing through to the global cache during integer stores. Local cache words are invalidated when data is written to the global cache during an army processor store.