Jack W Liu

7650464, Jan 19, 2010

Mar 26, 2007

11/728383

Jack Liu - San Jose CA, US

Intel Corporation - Santa Clara CA

G06F 12/00

711118, 711144, 711156, 711158, 711165, 707206, 718104, 718105

Data locality optimization through object relocation may be implemented in a virtual machine including a just-in-time compiler. The just-in-time compiler generates load instruction maps for each compiled method. A profile collector is coupled to the just-in-time compiler to receive hardware profiling support. The profile collector takes samples of data cache misses. A garbage collector is coupled to the profile collector. The garbage collector deduces types of objects from the cache miss samples and adjusts garbage collection object copying heuristics to relocate objects for better cache locality based on those types.

7730340, Jun 1, 2010

Feb 16, 2007

11/707844

Chunling Hu - Piscataway NJ, US
Jack Liu - San Jose CA, US

Intel Corporation - Santa Clara CA

G06F 1/26

713323, 713300, 713320

A machine learning technique is used to improve dynamic prediction of processor utilization for multi-threaded user-level applications in a dynamic run-time environment based on processor utilization history. Processor supply voltage and processor clock frequency may be dynamically scaled based on the predicted processor utilization in order to reduce processor power consumption.

7889530, Feb 15, 2011

Sep 14, 2007

11/855721

Robert Yu - Newark CA, US
Dave Trossen - Berkeley CA, US
Jack Liu - Santa Clara CA, US
Mukunda Krishnappa - Cupertino CA, US
Kevin James - Santa Clara CA, US

Agate Logic Inc. - Cupertino CA

G11C 15/00

365 49, 36518905, 36518907

A system for determining memory addresses including a first content-addressable memory (CAM) configured to generate a first matchvector based on a first key; a first inverse-mask-reverse (IMR) module operatively connected to the first CAM, where the first IMR module is configured to generate a first auxiliary matchvector based on the first matchvector; and a first priority encoder (PE) operatively connected to the first IMR module, where the first PE is configured to output a first encoded memory address based on the first auxiliary matchvector, where the first CAM, the first IMR module, and the first PE are associated with a first reconfigurable content-addressable memory (RCAM).

55617778, Oct 1, 1996

Aug 30, 1993

8/114552

Jack C. Liu - Rancho Palos Verdes CA
Ronald E. Rider - Menlo Park CA

Xerox Corporation - Stamford CT

G06F 1200
G06F 1300
G11C 800
G11C 700

395405

A process of loading an image in the form of a bit map into a memory which can transfer data words in burst mode in either row or column direction. First, the memory is divided into two sections with odd words stored in one section, even in the other, which allows ping pong buffers to be reading one word from memory while the next is being accessed. Also, the page height is set to be an odd number of words. Therefore, when the entire page is read in or out, successive words in either the row or column direction will always be alternately odd and even. If a partial image is read into the memory, this odd and even relationship will also hold. If an image with an even number of rows is read in, in order to preserve the sequential odd-even sequence, in every other column of the original data successive words are swapped so that the word order becomes 1, 0, 3, 2, etc. Then the addresses are also generated in staggered order, so that the words go into the correct location in memory. In this way, the word order of loading and reading of data is always successively odd and even regardless of the size of the image.