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Yee Kevin Ja

from Round Rock, TX
Age ~58
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Also known as:
Yee Goo Ja, Yee C Ja, Yee G Ja, Yee M Ja, Yee Gong Ja, Alex G Ja, Ja G Yee, Ja M Yee, Kevin Ja Yee, Ja Yee Kevin
Phone and address:
8000 Herbs Cave Cv, Round Rock, TX 78681
(512) 218-9920
Related to:
Alan W Moy, 67
Connected to:
Cindy M Ja, 56Dennis K Ja, 73Ham E Ja, 36Kimberly Ja, 34Mohamed Jaa, 40James R Jaacks, 60John W Jaacks, 96Abdalla M Jaafar, 32Aishah B Jaafar, 48Bassem M Jaafar, 58

Yee Ja Phones & Addresses

  • 8000 Herbs Cave Cv, Round Rock, TX 78681 (512) 218-9920
  • 1801 Warner Ranch Rd, Round Rock, TX 78664
  • Poughkeepsie, NY
  • Chicago, IL
  • Wappingers Falls, NY
  • Raleigh, NC
  • Kingston, NY

Work

Company: Ibm - Austin, TX 2008 Position: Cloud computing software engineer

Education

School / High School: University of Illinois at Urbana- Urbana-Champaign, IL Nov 2008 Specialities: B.S. in Computer Engineering

Skills

Linux • Aix • Shell Scripting • Unix • Perl • Unix Shell Scripting • Software Development • Virtualization • Software Engineering • Java • Solaris • Operating Systems • C/C++ Stl • Debugging • Eclipse • J2Ee Application Development • Junit • Object Oriented Design • Agile Methodologies • Xml • Kvm • Tcl • Flex • Bison • Awk • Sed • Python • Subversion • Computer Architecture • Distributed Systems • Software Design • Bash • Threads • Openssl • Git • Ipc • Sql

Industries

Computer Hardware

Resumes

Resumes

Yee Ja Photo 1

Yee Ja

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Location:
Austin, TX
Industry:
Computer Hardware
Skills:
Linux
Aix
Shell Scripting
Unix
Perl
Unix Shell Scripting
Software Development
Virtualization
Software Engineering
Java
Solaris
Operating Systems
C/C++ Stl
Debugging
Eclipse
J2Ee Application Development
Junit
Object Oriented Design
Agile Methodologies
Xml
Kvm
Tcl
Flex
Bison
Awk
Sed
Python
Subversion
Computer Architecture
Distributed Systems
Software Design
Bash
Threads
Openssl
Git
Ipc
Sql
Yee Ja Photo 2

Yee Ja Round Rock, TX

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Work:
IBM
Austin, TX
2008 to 2013
Cloud Computing Software Engineer
IBM
Austin, TX
1997 to 2007
Design Automation Software Engineer
Education:
University of Illinois at Urbana
Urbana-Champaign, IL
Nov 2008
B.S. in Computer Engineering

Publications

Us Patents

System And Method For Unfolding/Replicating Logic Paths To Facilitate Propagation Delay Modeling

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US Patent:
7302659, Nov 27, 2007
Filed:
Feb 10, 2005
Appl. No.:
11/054903
Inventors:
Yee Ja - Round Rock TX, US
Bradley S. Nelson - Austin TX, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/50
G06F 19/00
US Classification:
716 6, 716 7, 703 16
Abstract:
A system and method for unfolding/replicating logic paths to facilitate propagation delay modeling are provided. With the system and method, nets of an integrated circuit design are unfolded and logic of these nets is replicated such that each leg of a fanout can be driven independently from the signal source. In order to unfold the nets, the nets and logic are replicated in the netlist and connected to replicated source and endpoints. These new nets in the netlist may then be driven separately such that a different propagation delay along different nets from the same source may be simulated. In this way, a level of propagation delay may be abstracted into the modeling by driving or delaying each path separately. The transitioning value will then appear to have differing arrival times from the perspective of the sinks.

Modeling Asynchronous Behavior From Primary Inputs And Latches

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US Patent:
7447620, Nov 4, 2008
Filed:
Feb 23, 2006
Appl. No.:
11/360906
Inventors:
Zoltan T. Hidvegi - Round Rock TX, US
Yee Ja - Round Rock TX, US
Bradley S. Nelson - Austin TX, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/50
US Classification:
703 15
Abstract:
Asynchronous behavior of a circuit is emulated by modifying a netlist to insert additional logic at a driving element such as a latch. The additional logic outputs one of (i) a present output from the driving element, (ii) a delayed output from the driving element, or (iii) a random value, which drives downstream logic. The output of the additional logic is selectively responsive to a user-controlled skew enable input. The invention allows for simpler data skew logic transformations which are applicable to both latches and primary inputs, with no dependencies on any clock net.

Method And System For Unfolding/Replicating Logic Paths To Facilitate Modeling Of Metastable Value Propagation

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US Patent:
7448015, Nov 4, 2008
Filed:
May 19, 2006
Appl. No.:
11/419219
Inventors:
Yee Ja - Round Rock TX, US
Bradley S. Nelson - Austin TX, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/50
US Classification:
716 12, 716 6, 716 7
Abstract:
A net of an integrated circuit design is analyzed by unfolding paths on the receive side of an asynchronous boundary to facilitate modeling of the propagation of a metastable value from a receive latch to sinks of the net. The paths are unfolded by replicating combinational logic and wiring along the coincident portions to form non-intersecting, separate paths from the receive latch to two or more sinks. Common data or control inputs are provided for the gates in the replicated combinational logic. Driver logic may additionally be inserted along each replicated path, upstream of the combinational logic, to independently drive each of the sinks.

Clock-Gated Model Transformation For Asynchronous Testing Of Logic Targeted For Free-Running, Data-Gated Logic

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US Patent:
7453759, Nov 18, 2008
Filed:
Apr 26, 2006
Appl. No.:
11/380257
Inventors:
Yee Ja - Round Rock TX, US
Bradley S. Nelson - Austin TX, US
Wolfgang Roesner - Austin TX, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G11C 8/00
US Classification:
36523005, 36518904, 365191
Abstract:
Asynchronous behavior of a circuit is modeled by modifying latches in a netlist to add an extra port to the latches, e. g. , a single-port latch is transformed into a dual-port latch. Each input port has an enable line and a data input. The data input in the added port is a feedback line from the latch output, and the enable line in the added port is the logical NOR of all of the original enable lines. By adding this extra latch port in the higher-level model, it becomes possible to introduce assertion logic to ensure that one and only one latch port for a given latch is ever active during the same simulation cycle. The model can then be tested earlier in the design methodology prior to the availability of the post-synthesis netlist. The model can also be used in both simulation and formal or semi-formal verification.

Method For Modeling Metastability Decay Through Latches In An Integrated Circuit Model

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US Patent:
7484192, Jan 27, 2009
Filed:
Sep 18, 2006
Appl. No.:
11/532575
Inventors:
Yee Ja - Round Rock TX, US
Bradley S. Nelson - Austin TX, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/50
G06F 9/45
US Classification:
716 5, 716 6, 703 13, 703 14
Abstract:
Mechanisms for modeling metastability decay through latches in an integrated circuit model are provided. Asynchronous clock boundaries are identified in the integrated circuit model and latches in a receive clock domain are enumerated. Latches within a range of the asynchronous clock boundary are selected for transformation. These latches are transformed into metastability decay latches using new latch primitive logic that models the decay of an indeterminate value. The metastability decay latches maintains an indeterminate value during a metastability time period and achieve a randomly selected logic value at the end of the metastability time period. The transformed integrated circuit model may then be simulated and the results analyzed to generate reports of the integrated circuit model's operation. The transformed integrate circuit model more accurately represents the actual operation of the hardware implementation of the integrated circuit model.

Method For Asynchronous Clock Modeling In An Integrated Circuit Simulation

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US Patent:
7484196, Jan 27, 2009
Filed:
Sep 18, 2006
Appl. No.:
11/532582
Inventors:
Yee Ja - Round Rock TX, US
Bradley S. Nelson - Austin TX, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/50
G06F 9/45
US Classification:
716 6, 703 19
Abstract:
Mechanisms for asynchronous clock modeling in an integrated circuit simulation are provided. The mechanisms of the illustrative embodiments provide clock skewing logic for phase shifting a clock signal in an integrated circuit design. This clock skewing logic adds delay to one or more clocks of an integrated circuit design to thereby place that clock out of phase with other clocks in the integrated circuit design. In one illustrative embodiment, delay is introduced into a clock net in an increasing manner with each enablement of the clock skewing logic. In another illustrative embodiment, the introduced delay is increased and decreased within a window from no phase shift of the clock net up to a maximum phase shift of the clock net. Once the maximum phase shift is reached, the amount of delay introduced is decreased with subsequent enablement of the clock skewing logic.

Method For Driving Values To Dc Adjusted/Untimed Nets To Identify Timing Problems

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US Patent:
7490305, Feb 10, 2009
Filed:
Jul 17, 2006
Appl. No.:
11/457865
Inventors:
Robert B. Gass - Pflugerville TX, US
Yee Ja - Round Rock TX, US
Christoph Jaeschke - Tuebingen, DE
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/50
US Classification:
716 4, 716 5, 716 6
Abstract:
A method for driving values to “don't care” (DC) adjusted/untimed nets of an integrated circuit design to thereby identify timing problems are provided. The system and method may be utilized, for example, with logical built-in self test (LBIST) testing of an integrated circuit in which the DC adjusted (dcadj) nets for normal functional mode of the integrated circuit may not be DC adjusted for LBIST mode. By using the system and method, timing related problems associated with DC adjusted/untimed nets can be made apparent either by using simulation or semi-formal/formal analysis. For example, with regard to DC adjusted/untimed nets, the system and method may identify any violations of these nets with regard to maintaining their DC adjusted values. Such identification of violations of DC adjusted/untimed nets may be made without interfering with the static timing analysis of timed nets.

Method For Propagating Phase Constants In Static Model Analysis Of Circuits

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US Patent:
7519928, Apr 14, 2009
Filed:
Jun 1, 2006
Appl. No.:
11/421578
Inventors:
Yee Ja - Round Rock TX, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 9/45
G06F 17/50
US Classification:
716 5
Abstract:
A method for propagating phase constants for static circuit model analysis is provided. The mechanisms of the illustrative embodiments make use of multiple phases of constant propagation to handle sequential elements in a circuit model. The phases are determined based on an oscillating clock input. In one exemplary embodiment, the number of phases is determined based on a least common denominator of the periodicity of the input clocks of nets in the circuit model. The static analysis is performed for each phase taking into consideration the results of a previous phase of the static analysis with regard to sequential elements of the circuit. Results may be output for verification of the circuit design.
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Yee Kevin Ja from Round Rock, TX, age ~58 Get Report