In Sook Kim

6346827, Feb 12, 2002

Aug 4, 1999

09/366937

Wayne Yeung - San Francisco CA
Chiakang Sung - Milpitas CA
Myron W. Wong - Fremont CA
Khai Nguyen - San Jose CA
Bonnie I. Wang - Cupertino CA
Xiaobao Wang - Santa Clara CA
Joseph Huang - San Jose CA
In Whan Kim - San Jose CA

Altera Corporation - San Jose CA

H01L 2500

326 41, 326 50, 326 45

A programmable input/output circuit for a programmable logic device input/output pin can be configured in a standard I/O mode, or in a reference voltage mode. The circuit includes a tristatable, but otherwise standard I/O buffer as well as a reference voltage clamp circuit. In reference voltage mode, the I/O circuit is tristated, and the reference voltage clamp circuit passes a reference voltage from the I/O pin to a reference voltage bus. In standard I/O mode, the I/O buffer is operational. The reference voltage clamp circuit isolates the I/O pin from the reference voltage bus and may include undervoltage and overvoltage protection to prevent disturbance of the reference voltage bus by an out-of-range I/O signal.

6369624, Apr 9, 2002

Nov 2, 1999

09/432142

Bonnie I. Wang - Cupertino CA
Joseph Huang - San Jose CA
Chiakang Sung - Milpitas CA
Xiaobao Wang - Santa Clara CA
In Whan Kim - San Jose CA
Wayne Yeung - San Francisco CA
Khai Nguyen - San Jose CA

Altera Corporation - San Jose CA

H03L 706

327156, 327147, 327150, 327159, 331 25, 331 60

A circuit provides a programmable phase shift feature, where the phase shift is programmably selectable by a user. This circuitry may be incorporated in a programmable logic device (PLD) or field programmable gate array (FPGA) to provide additional programmability features. The programmable phase shift circuitry may be implemented within a phase locked loop (PLL) or delay locked loop (DLL) circuit.

6400598, Jun 4, 2002

Apr 25, 2001

09/843299

Khai Nguyen - San Jose CA
Xiaobao Wang - Santa Clara CA
In Whan Kim - San Jose CA
Chiakang Sung - Milpitas CA
Richard G. Cliff - Milpitas CA
Joseph Huang - San Jose CA
Bonnie I. Wang - Cupertino CA
Wayne Yeung - San Francisco CA

Altera Corporation - San Jose CA

G11C 506

365 63, 326 39

A programmable logic device is equipped for low voltage differential signaling (âLVDSâ) by providing an LVDS input buffer and/or an LVDS output buffer on the device. I/O pins on the device that are used together in pairs for LVDS can alternatively be used individually for other types of signaling. The LVDS buffers are constructed to give good performance and to meet LVDS specifications despite variations due to temperature, manufacturing process inconsistency, and power supply changes.

6433579, Aug 13, 2002

May 22, 2001

09/863143

Bonnie I. Wang - Cupertino CA
Chiakang Sung - Milpitas CA
Yan Chong - Stanford CA
Philip Pan - Fremont CA
Khai Nguyen - San Jose CA
Joseph Huang - San Jose CA
Xiaobao Wang - Santa Clara CA
In Whan Kim - San Jose CA
Gopinath Rangan - Santa Clara CA

Altera Corporation - San Jose CA

H03K 19177

326 38, 326 41, 326 86, 326 90

A programmable logic device is equipped for various differential signaling schemes by providing a differential output buffer on the device that can be configured according to the needs of the particular differential signaling schemes that may be used. The buffer includes a differential output driver, an adjustable current limiting circuit between the supply voltage and the differential output driver, and an adjustable current limiting circuit between the differential output driver and ground. By selectively adjusting the two current limiting circuits, the output impedance and current, as well as the common mode output voltage and the differential output voltage can be controlled.

6448820, Sep 10, 2002

Nov 2, 1999

09/432442

Xiaobao Wang - Santa Clara CA
Chiakang Sung - Milpitas CA
Joseph Huang - San Jose CA
Bonnie I. Wang - Cupertino CA
Khai Nguyen - San Jose CA
Wayne Yeung - San Francisco CA
In Whan Kim - San Jose CA

Altera Corporation - San Jose CA

H03D 1300

327 12, 327 5, 327 40, 327 43, 326 96

A phase frequency detector (PFD) circuit ( ) compares two clock signals and generates a number of outputs to indicate a phase difference between these two clock signals ( ). The phase frequency detector has more than three states. The PFD circuit may be used in phase locked loop (PLL) or delay locked loop (DLL) circuit in order to maintain or lock a phase relationship between the two clock signals. The PFD circuitry will allow for a fast lock acquisition time, even when there is a relatively wide frequency range between the two clock signals.

6535031, Mar 18, 2003

May 13, 2002

10/146438

Khai Nguyen - San Jose CA
Xiaobao Wang - Santa Clara CA
In Whan Kim - San Jose CA
Chiakang Sung - Milpitas CA
Richard G Cliff - Milpitas CA
Joseph Huang - San Jose CA
Bonnie I Wang - Cupertino CA
Wayne Yeung - San Francisco CA

Altera Corporation - San Jose CA

H03K 522

327 65, 327 66, 330253

A programmable logic device is equipped for low voltage differential signaling (âLVDSâ) by providing an LVDS input buffer and/or an LVDS output buffer on the device. I/O pins on the device that are used together in pairs for LVDS can alternatively be used individually for other types of signaling. The LVDS buffers are constructed to give good performance and to meet LVDS specifications despite variations due to temperature, manufacturing process inconsistency, and power supply changes.

6549045, Apr 15, 2003

Jan 11, 2002

10/043620

Bonnie Wang - Cupertino CA
Chiakang Sung - Milpitas CA
Khai Nguyen - San Jose CA
Joseph Huang - San Jose CA
Xiaobao Wang - Santa Clara CA
In Whan Kim - San Jose CA
Gopi Rangan - Santa Clara CA
Yan Chong - Stanford CA
Phillip Pan - Freemont CA

Altera Corporation - San Jose CA

H03K 2100

327115, 327117, 377 47, 377 48

A digital, preferably programmable, circuit is disclosed for providing one or more clock signals with variable frequency and/or phase. The clock signals exhibit a low amount of skew relative to other clock signals and data signals provided by the circuit. In one embodiment, the circuit includes a plurality of channels each having a parallel-in/serial-out shift register, a flip-flop, and a delay circuit. The shift register can receive data bits in data channels or clock frequency select bits in frequency-divided clock channels. The serial output from the register acts as an input for the flip flop, both of which are triggered by an input reference clock. The delay circuit delays the input reference clock. In each channel, a multiplexer is configured to select the clock or data channel output from the register, flip-flop, and delay circuit outputs. Since the delays in all output paths are matched, skew is minimized.

6617884, Sep 9, 2003

May 28, 2002

10/160355

Xiaobao Wang - Santa Clara CA
Chiakang Sung - Milpitas CA
Joseph Huang - San Jose CA
Bonnie I. Wang - Cupertino CA
Khai Nguyen - San Jose CA
Wayne Yeung - San Francisco CA
In Whan Kim - San Jose CA

Altera Corporation - San Jose CA

H03D 1300

327 12, 327 3, 327 7

A phase frequency detector (PFD) circuit ( ) compares two clock signals and generates a number of outputs to indicate a phase difference between these two clock signals ( ). The phase frequency detector has more than three states. The PFD circuit may be used in phase locked loop (PLL) or delay locked loop (DLL) circuit in order to maintain or lock a phase relationship between the two clock signals. The PFD circuitry will allow for a fast lock acquisition time, even when there is a relatively wide frequency range between the two clock signals.