Il Ki Lee

7683369, Mar 23, 2010

Apr 10, 2008

12/100554

Moses Ho - Campbell CA, US
Tiesheng Li - San Jose CA, US
Il Kwan Lee - San Jose CA, US

Alpha & Omega Semiconductor, Inc. - Sunnyvale CA

H01L 21/66

257 48, 257E21521, 438 18

A structure is disclosed for measuring body pinch resistance Rp of trench MOSFET arrays on a wafer. The trench MOSFET array has a common drain layer of first conductivity type and a 2D-trench MOSFET array atop the common drain layer. The 2D-trench MOSFET array has an interdigitated array of source-body columns and gate trench columns. Each source-body column has a bottom body region of second conductivity type with up-extending finger structures. Each source-body column has top source regions of first conductivity type bridging the finger structures. The structure includes:a) A source-body column wherein each finger structure of the bottom body region has a formed top contact electrode. b) Two gate trench columns flank the source-body column and both have a formed top common gate contact electrode. Upon connection of the structure to external voltage/current measurement devices, Rp can be measured while mimicking the parasitic effect of neighboring trench MOSFETs.

8067304, Nov 29, 2011

Jan 20, 2009

12/356077

Il Kwan Lee - San Ramon CA, US

Alpha and Omega Semiconductor, Inc. - Sunnyvale CA

H01L 21/20

438584, 438654, 438655, 438656, 438688, 257330, 257331, 257E21584

A method is disclosed for forming a patterned thick metallization atop a semiconductor chip wafer. The method includes fabricating a nearly complete semiconductor chip wafer ready for metallization; depositing a bottom metal layer of sub-thickness TK together with its built-in alignment mark using a hot metal process; depositing a top metal layer of sub-thickness TK using a cold metal process thus forming a stacked thick metallization of total thickness TK=TK+TK; then, use the built-in alignment mark as reference, patterning the stacked thick metallization. A patterned thick metallization is thus formed with the advantages of better metal step coverage owing to the superior step coverage nature of the hot metal process as compared to the cold metal process; and lower alignment error rate owing to the lower alignment signal noise nature of the cold metal process as compared to the hot metal process.

8193580, Jun 5, 2012

Aug 14, 2009

12/583191

John Chen - Palo Alto CA, US
Il Kwan Lee - San Ramon CA, US
Hong Chang - Cupertino CA, US
Wenjun Li - Shanghai, CN
Anup Bhalla - Santa Clara CA, US
Hamza Yilmaz - Saratoga CA, US

Alpha and Omega Semiconductor, Inc. - Sunnyvale CA

H01L 29/78

257331, 257E29257

A semiconductor device embodiment includes a substrate, an active gate trench in the substrate, and an asymmetric trench in the substrate. The asymmetric trench has a first trench wall and a second trench wall, the first trench wall is lined with oxide having a first thickness, and the second trench wall is lined with oxide having a second thickness that is different from the first thickness. Another semiconductor device embodiment includes a substrate, an active gate trench in the substrate; and a source polysilicon pickup trench in the substrate. The source polysilicon pickup trench includes a polysilicon electrode, and top surface of the polysilicon electrode is below a bottom of a body region. Another semiconductor device includes a substrate, an active gate trench in the substrate, the active gate trench has a first top gate electrode and a first bottom source electrode, and a gate runner trench comprising a second top gate electrode and a second bottom source electrode. The second top gate electrode is narrower than the second bottom source electrode.

8236651, Aug 7, 2012

Aug 14, 2009

12/583192

John Chen - Palo Alto CA, US
Il Kwan Lee - San Ramon CA, US
Hong Chang - Cupertino CA, US
Wenjun Li - Shanghai, CN
Anup Bhalla - Santa Clara CA, US
Hamza Yilmaz - Saratoga CA, US

Alpha and Omega Semiconductor Incorporated - Sunnyvale CA

H01L 21/8234

438270, 257E21629

A method for fabricating a semiconductor device includes forming a plurality of trenches, including applying a first mask, forming a first polysilicon region in at least some of the plurality of trenches, forming a inter-polysilicon dielectric region and a termination protection region, including applying a second mask, forming a second polysilicon region in the at least some of the plurality of trenches, forming a first electrical contact to the first polysilicon region and forming a second electrical contact to the second polysilicon region, including applying a third mask, disposing a metal layer, and forming a source metal region and a gate metal region, including applying a fourth mask.

8288273, Oct 16, 2012

Oct 17, 2011

13/274607

Il Kwan Lee - San Ramon CA, US

Alpha & Omega Semiconductor Inc. - Sunnyvale CA

H01L 21/4763

438643, 438626, 438627, 438648, 438652, 438688, 257E21582

A method is disclosed for forming a patterned thick metallization atop a semiconductor chip wafer. The method includes fabricating a nearly complete semiconductor chip wafer ready for metallization; depositing a bottom metal layer of sub-thickness TK together with its built-in alignment mark using a hot metal process; depositing a top metal layer of sub-thickness TK using a cold metal process thus forming a stacked thick metallization of total thickness TK=TK+TK; then, use the built-in alignment mark as reference, patterning the stacked thick metallization. A patterned thick metallization is thus formed with the advantages of better metal step coverage owing to the superior step coverage nature of the hot metal process as compared to the cold metal process; and lower alignment error rate owing to the lower alignment signal noise nature of the cold metal process as compared to the hot metal process.

8354334, Jan 15, 2013

Oct 21, 2011

13/279094

Il Kwan Lee - San Ramon CA, US

Alpha & Omega Semiconductor Inc. - Sunnyvale CA

H01L 21/20

438584, 438652, 438654, 438655, 438688, 257330, 257331, 257341, 257E21582

A method is disclosed for forming a patterned thick metallization atop a semiconductor chip wafer. The method includes fabricating a nearly complete semiconductor chip wafer ready for metallization; depositing a bottom metal layer of sub-thickness TK together with its built-in alignment mark using a hot metal process; depositing a top metal layer of sub-thickness TK using a cold metal process thus forming a stacked thick metallization of total thickness TK=TKTK; then, use the built-in alignment mark as reference, patterning the stacked thick metallization. A patterned thick metallization is thus formed with the advantages of better metal step coverage owing to the superior step coverage nature of the hot metal process as compared to the cold metal process; and lower alignment error rate owing to the lower alignment signal noise nature of the cold metal process as compared to the hot metal process.

8564055, Oct 22, 2013

Apr 26, 2012

13/456406

John Chen - Palo Alto CA, US
Il Kwan Lee - San Ramon CA, US
Hong Chang - Cupertino CA, US
Wenjun Li - Shanghai, CN
Anup Bhalla - Santa Clara CA, US
Hamza Yilmaz - Saratoga CA, US

Alpha and Omega Semiconductor Incorporated - Sunnyvale CA

H01L 29/78

257331

A semiconductor device includes a substrate, an active gate trench in the substrate, the active gate trench has a first top gate electrode and a first bottom source electrode, and a gate runner trench comprising a second top gate electrode and a second bottom source electrode. The second top gate electrode is narrower than the second bottom source electrode.

20140037846, Feb 6, 2014

Jul 16, 2013

13/943523

Il Song Lee - San Jose CA, US

B05C 3/00
B05D 1/00

42725528, 118724, 4272555

Heating of precursor before exposing the substrate to the precursor for depositing material on the substrate using a deposition method (e.g., ALD, MLD or CVD). A reactor for injecting precursor onto the substrate includes a heater placed in a path between a channel connected to a source of the precursor and a reaction chamber of the reactor. As the precursor passes the heater, the precursor is heated to a temperature conducive to the deposition process. Alternatively or in addition to the heater, the reactor may inject a heated gas that mixes with the precursor to increase the temperature of the precursor before exposing the substrate to the precursor.