Hyun Joo Yi

8620977, Dec 31, 2013

Aug 7, 2013

13/961534

Martin Langhammer - Salisbury, GB
Yi-Wen Lin - Glendale CA, US
Wai-Bor Leung - Milpitas CA, US
David Lewis - Toronto, CA
Volker Mauer - Princes Risborough, GB
Henry Y. Lui - Millbrae CA, US
Suleyman Sirri Demirsoy - London, GB
Hyun Yi - San Jose CA, US

Altera Corporation - San Jose CA

G06F 7/38
G06F 7/00

708230, 708200, 708203, 708490, 708503

Digital signal processing (“DSP”) circuit blocks are provided that can more easily work together to perform larger (e. g. , more complex and/or more arithmetically precise) DSP operations if desired. These DSP blocks may also include redundancy circuitry that facilitates stitching together multiple such blocks despite an inability to use some block (e. g. , because of a circuit defect). Systolic registers may be included at various points in the DSP blocks to facilitate use of the blocks to implement systolic form, finite-impulse-response (“FIR”), digital filters.

20140082035, Mar 20, 2014

Nov 21, 2013

14/086328

Martin Langhammer - Alderbury, GB
Yi-Wen Lin - Glendale CA, US
Wai-Bor Leung - Milpitas CA, US
David Lewis - Toronto, CA
Volker Mauer - Lacey Green, GB
Henry Y. Lui - Millbrae CA, US
Suleyman Sirri Demirsoy - London, GB
Hyun Yi - San Jose CA, US

Altera Corporation - San Jose CA

G06F 17/10

708203

Digital signal processing (“DSP”) circuit blocks are provided that can more easily work together to perform larger (e.g., more complex and/or more arithmetically precise) DSP operations if desired. These DSP blocks may also include redundancy circuitry that facilitates stitching together multiple such blocks despite an inability to use some block (e.g., because of a circuit defect). Systolic registers may be included at various points in the DSP blocks to facilitate use of the blocks to implement systolic form, finite-impulse-response (“FIR”), digital filters.

20200026493, Jan 23, 2020

Sep 27, 2019

16/586693

- San Jose CA, US
Martin Langhammer - Alderbury, GB
Yi-Wen Lin - Glendale CA, US
Hyun Yi - San Jose CA, US

G06F 7/483
G06F 7/487
G06F 7/485
G06F 7/499

Configurable specialized processing blocks, such as DSP blocks, are described that implement fixed and floating-point functionality in a single mixed architecture on a programmable device. The described architecture reduces the need to construct floating-point functions outside the configurable specialized processing block, thereby minimizing hardware cost and area. The disclosed architecture also introduces pipelining into the DSP block in order to ensure the floating-point multiplication and addition functions remain in synchronicity, thereby increasing the maximum frequency at which the DSP block can operate. Moreover, the disclosed architecture includes logic circuitry to support floating-point exception handling.