Hyun Sook Lee

6794899, Sep 21, 2004

Sep 4, 2002

10/235981

Hyun Lee - Ladera Ranch CA
Trevor Edward Little - Allentown PA

Agere Systems Inc. - Allentown PA

H03K 1900

326 59, 326 83, 326 82, 326 21

Multiple level logic bus drivers and receivers communicate over a bus using a multiple-level logic protocol that transfers multiple bits on each signal wire of a bus in a given interval without increasing the bus width or power dissipation. In one embodiment, four logic levels are employed using CMOS transistor circuitry operating with low voltage (e. g. , 1. 2V or 1. 3V) power supplies (V ) and P and N transistor threshold voltage levels of V and V on the order of 0. 4--0. 5V. Thus, the separation between the following four logic levels is approximately uniform: V ; V -V ; V +V ; and V. The approximately equal voltage gaps between each quantization level provide uniform noise margins for all levels. A bus noise minimization scheme and a quick recovery scheme ensure the correct data transfer in the presence of injected noise. An initial over drive feature is disclosed for shorter transition times.

7174475, Feb 6, 2007

Feb 16, 2001

09/785604

Hyun Lee - Ladera Ranch CA, US
Han Nguyen - Allentown PA, US
Lai Q. Pham - San Diago CA, US

Agere Systems Inc. - Allentown PA

G06F 1/04

713503, 713400, 713600, 327233

A method and apparatus are disclosed for dynamically reducing clock skew among various nodes on an integrated circuit. The disclosed clock skew reduction technique dynamically estimates the clock delay to each node and inserts a corresponding delay for each node such that the clock signals arriving at each node are all in phase with a global clock (or 180 out of phase). Delays attributable to both the wire RC delays and the clock buffer delays are addressed. A feedback path for the clock signal associated with each node allows the round trip travel time of the clock signal to be estimated. When the length of the feedback path matches the length of the primary clock path, the clock skew present at the corresponding node can be estimated as fifty percent (50%) of the round trip delay time. Dynamic adjustments to the delay control circuit are permitted as operating conditions shift. Clock signals arriving at individual nodes on the integrated circuit remain in phase with the global PLL clock (PCK), regardless of variations in the operating voltage or temperature (or both).

7672271, Mar 2, 2010

Dec 21, 2006

11/644182

Hyun Lee - Ladera Ranch CA, US

H04W 4/00

370328, 370536, 370338

In accordance with the present invention, there is provided a high-speed wireless backbone connection, Backbone Connection Facilitator (BCF), to create a wireless home network, which may consist of many short-range wired/wireless networks. BCF dynamically creates concurrent data pipelines to meet the data bandwidth demand to transfer packets from one short-range wired/wireless network to another. BCF employs the newly developed antenna technologies (ex. MIMO, SDMA) to minimize the transmit power, to reduce the interferences, and to support the real time communication. BCF contains the BCF-PHY layer, the BCF-Data-Link-Layer, and the BCF-Network-Layer. The BCF-PHY layer consists of antenna array, a PHY Base Band controller, and a digital beam former. The BCF-Data-Link-Layer provides the MAC functionality. The BCF-Network-Layer assembles the packet, provides the source and destination address, and provides the BCF-PHY beam forming information.

8001434, Aug 16, 2011

Apr 13, 2009

12/422925

Hyun Lee - Ladera Ranch CA, US
Jayesh R. Bhakta - Cerritos CA, US
Soonju Choi - Irvine CA, US

NETLIST, Inc. - Irvine CA

G01R 31/28
G11C 29/00

714733, 714719

A self-testing memory module includes a printed circuit board configured to be operatively coupled to a memory controller of a computer system and includes a plurality of memory devices on the printed circuit board, each memory device of the plurality of memory devices comprising data, address, and control ports. The memory module also includes a control module configured to generate address and control signals for testing the memory devices. The memory module includes a data module comprising a plurality of data handlers. Each data handler is operable independently from each of the other data handlers of the plurality of data handlers. Each data handler is operatively coupled to a corresponding plurality of the data ports of one or more of the memory devices and is configured to generate data for writing to the corresponding plurality of data ports.

8154901, Apr 10, 2012

Apr 13, 2009

12/422853

Hyun Lee - Ladera Ranch CA, US
Jayesh R. Bhakta - Cerritos CA, US
Jeffrey C. Solomon - Irvine CA, US
Mario Jesus Martinez - Laguna Niguel CA, US
Chi-She Chen - Walnut CA, US

Netlist, Inc. - Irvine CA

G11C 5/02

365 51, 326 30, 365191, 365198, 36523005

Certain embodiments described herein include a memory module having a printed circuit board including at least one connector configured to be operatively coupled to a memory controller of a computer system. The memory module further includes a plurality of memory devices on the printed circuit board and a circuit including a first set of ports operatively coupled to at least one memory device. The circuit further includes a second set of ports operatively coupled to the at least one connector. The circuit includes a switching circuit configured to selectively operatively couple one or more ports of the second set of ports to one or more ports of the first set of ports. Each port of the first set and the second set comprises a correction circuit which reduces noise in one or more signals transmitted between the first set of ports and the second set of ports.

8264903, Sep 11, 2012

May 5, 2010

12/774632

Hyun Lee - Ladera Ranch CA, US
Jayesh R. Bhakta - Cerritos CA, US

Netlist, Inc. - Irvine CA

G11C 7/00

365222, 365194, 36523313

A memory module according to certain aspects has a plurality of memory devices arranged into one or more logical ranks. Each logical rank may correspond to a set of at least two physical ranks. The memory module can include a circuit operatively coupled to the plurality of memory devices and configured to be operatively coupled to a memory controller of a computer system to receive a logical rank refresh command. In response, the circuit can initiate a first refresh operation for one or more first physical ranks and then initiate a second refresh operation for one or more second physical ranks. The memory module can further include a memory location storing a refresh time (tRFC) value accessible by the memory controller and based at least in part on a calculated maximum amount of time for refreshing the logical rank.

8359501, Jan 22, 2013

Jul 14, 2011

13/183253

Hyun Lee - Ladera Ranch CA, US
Jayesh R. Bhakta - Cerritos CA, US
Soonju Choi - Irvine CA, US

Netlist, Inc. - Irvine CA

G11C 29/00

714719, 714718

A self-testing memory module includes a printed circuit board configured to be operatively coupled to a memory controller of a computer system and includes a plurality of memory devices on the printed circuit board, each memory device of the plurality of memory devices comprising data, address, and control ports. The memory module also includes a control module configured to generate address and control signals for testing the memory devices. The memory module includes a data module comprising a plurality of data handlers. Each data handler is operable independently from each of the other data handlers of the plurality of data handlers. Each data handler is operatively coupled to a corresponding plurality of the data ports of one or more of the memory devices and is configured to generate data for writing to the corresponding plurality of data ports.

8417870, Apr 9, 2013

Jul 16, 2009

12/504131

Hyun Lee - Ladera Ranch CA, US
Jayesh R. Bhakta - Cerritos CA, US

Netlist, Inc. - Irvine CA

G06F 12/00
G06F 13/00

711 5, 711100, 711154

A load-reducing memory module includes a plurality of memory components such as DRAMs. The memory components are organized into sets or ranks such that they can be accessed simultaneously for the full data bit-width of the memory module. A plurality of load reducing switching circuits is used to drive data bits from a memory controller to the plurality of memory components. The load reducing switching circuits are also used to multiplex the data lines from the memory components and drive the data bits to the memory controller.