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Hung Fai Ng

from New York, NY
Age ~70
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Also known as:
Hung F Ng, Hung Chao Ng, Hung C Ng, Hung A Ng, Mun Sheung Ng, Mun S Ng, Mon Sheung Ng, Hung Ng Fai, Hung Faing, Hungfai Ng
Phone and address:
109 Lafayette St, New York, NY 10013
(212) 226-2923
Related to:
Man M Ng, 71Hui K Ng, 52Alan NgYing W Ng, 62
Connected to:
Adela A Ng, 61Alec K Ng, 69Alina Ng, 51Allison Y Ng, 48Amoy Ng, 78Andrea K Ng, 56Andres Ng, 27Angel Y Ng, 63Antonio C Ng, 77Ariel Ng, 30

Hung Ng Phones & Addresses

  • 109 Lafayette St, New York, NY 10013 (212) 226-2923
    • s
  • 216 E 47Th St #22A, New York, NY 10017
  • 6430 211Th St APT 64, Oakland Gdns, NY 11364
  • Flushing, NY
  • Brooklyn, NY

Work

Company: Hung Fai Ng MD Address: 109 Lafayette St Suite 206, New York, NY 10013 Phones: (212) 226-2923

Education

School / High School: Central University of Este (Uce) / School of Medicine

Languages

English • Chinese

Awards

Healthgrades Honor Roll

Ranks

Certificate: Internal Medicine, 2006

Specialities

Internal Medicine

Professional Records

Medicine Doctors

Hung Ng Photo 1

Dr. Hung F Ng, New York NY - MD (Doctor of Medicine)

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Specialties:
Internal Medicine
Address:
Hung Fai Ng MD
109 Lafayette St Suite 206, New York, NY 10013
(212) 226-2923 (Phone)
Certifications:
Internal Medicine, 2006
Awards:
Healthgrades Honor Roll
Languages:
English
Chinese
Education:
Medical School
Central University of Este (Uce) / School of Medicine
Medical School
Jersey City Medical Center
Hung Ng Photo 2

Hung F. Ng

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Specialties:
Internal Medicine
Work:
Hung Fai Ng MD
109 Lafayette St RM 206, New York, NY 10013
(212) 226-2923 (phone), (212) 343-2184 (fax)
Education:
Medical School
Univ Central Del Este (uce), Fac De Med, San Pedro De Macoris, Dom Republic
Graduated: 1981
Procedures:
Arthrocentesis
Continuous EKG
Destruction of Benign/Premalignant Skin Lesions
Electrocardiogram (EKG or ECG)
Pulmonary Function Tests
Vaccine Administration
Conditions:
Abdominal Aortic Aneurysm
Abdominal Hernia
Abnormal Vaginal Bleeding
Acute Pharyngitis
Alzheimer's Disease
Languages:
Chinese
English
Description:
Dr. Ng graduated from the Univ Central Del Este (uce), Fac De Med, San Pedro De Macoris, Dom Republic in 1981. He works in New York, NY and specializes in Internal Medicine. Dr. Ng is affiliated with New York Presbyterian Lower Manhattan Hospital.
Hung Ng Photo 3

Hung Fai Ng, New York NY

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Specialties:
Internist
Address:
109 Lafayette St, New York, NY 10013
Education:
Eastern Central University, Faculty of Medicine - Doctor of Medicine
Jersey City Medical Center - Residency - Internal Medicine
Board certifications:
American Board of Internal Medicine Certification in Internal Medicine

Resumes

Resumes

Hung Ng Photo 4

Hung Ng

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Location:
United States
Hung Ng Photo 5

Hung Ng

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Location:
United States

Business Records

Name / Title
Company / Classification
Phones & Addresses
Hung M. Ng
Principal
Ng, Ki Gee
Operates Apartment Building
41 Henry St, New York, NY 10002
Hung Fai Ng
Internal Medicine, Medical Doctor
Fai, Ng Hung
Medical Doctor's Office
109 Lafayette St, New York, NY 10013
Hung Fai Ng
Chung, Dr. Susey
Internist
123 Lafayette St, New York, NY 10013
(212) 334-1207
Hung Yip Ng
ECSTASY BAR CORP
7214 New Utrecht Ave, Brooklyn, NY 11228

Publications

Us Patents

Method And Structure To Use An Etch Resistant Liner On Transistor Gate Structure To Achieve High Device Performance

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US Patent:
7064027, Jun 20, 2006
Filed:
Nov 13, 2003
Appl. No.:
10/713227
Inventors:
Hung Y. Ng - New Milford NJ, US
Haining S. Yang - Wappingers Falls NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 21/8234
US Classification:
438238, 438199, 438382, 438216
Abstract:
An etch resistant liner covering sidewalls of a transistor gate stack and along a portion of the substrate at a base of the transistor gate stack. The liner prevents silicide formation on the sidewalls of the gate stack, which may produce electrical shorting, and determines the location of silicide formation within source and drain regions within the substrate at the base of the transistor gate stack. The liner also covers a resistor gate stack preventing silicide formation within or adjacent to the resistor gate stack.

Structure To Use An Etch Resistant Liner On Transistor Gate Structure To Achieve High Device Performance

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US Patent:
7307323, Dec 11, 2007
Filed:
Mar 7, 2006
Appl. No.:
11/369409
Inventors:
Hung Y. Ng - New Milford NJ, US
Haining S. Yang - Wappingers Falls NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 29/76
US Classification:
257389, 257410
Abstract:
An etch resistant liner covering sidewalls of a transistor gate stack and along a portion of the substrate at a base of the transistor gate stack. The liner prevents silicide formation on the sidewalls of the gate stack, which may produce electrical shorting, and determines the location of silicide formation within source and drain regions within the substrate at the base of the transistor gate stack. The liner also covers a resistor gate stack preventing silicide formation within or adjacent to the resistor gate stack.

Method For Polysilicon Conductor (Pc) Trimming For Shrinking Critical Dimension And Isolated-Nested Offset Correction

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US Patent:
20020142252, Oct 3, 2002
Filed:
Mar 29, 2001
Appl. No.:
09/821478
Inventors:
Hung Ng - New Milford NJ, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G03F007/36
C23F001/00
US Classification:
430/313000, 430/311000, 430/312000, 430/318000, 216/058000
Abstract:
A method of forming a semiconductor device, includes providing a structure having a first critical dimension, forming a lithographic pattern on the structure, and etching the structure with an O-containing material to trim the first critical dimension to a second critical dimension, the second critical dimension being smaller than the first critical dimension. Thereafter, any offset between the nested features and the isolated feature can be corrected.

Method And Structure To Use An Etch Resistant Liner On Transistor Gate Structure To Achieve High Device Performance

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US Patent:
20080036017, Feb 14, 2008
Filed:
Aug 9, 2007
Appl. No.:
11/836193
Inventors:
Hung Ng - New Milford NJ, US
Haining Yang - Wappingers Falls NY, US
International Classification:
H01L 31/00
US Classification:
257412000, 257E29128
Abstract:
A semiconductor device. The semiconductor device includes a substrate includes: a substrate having a first gate stack on a surface of the substrate, wherein the first gate stack has a top surface parallel to the surface of the substrate and sidewalls perpendicular to the surface of the substrate; an etch resistant first liner over the sidewalls of the first gate stack and not over the top surface of the first gate stack; a first outer spacer over the first liner, wherein the first liner is disposed between the first outer spacer and the sidewalls of the first gate stack, and wherein a portion of the first liner covers a first portion of the surface of the substrate; an insulative layer on a second portion of the surface of the substrate; and a conductive layer on the top surface of the first gate stack.

Complementary Metal-Oxide-Semiconductor Device With Embedded Stressor

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US Patent:
20090242989, Oct 1, 2009
Filed:
Mar 25, 2008
Appl. No.:
12/054933
Inventors:
KEVIN K. CHAN - Staten Island NY, US
Jack O. Chu - Manhasset Hills NY, US
Jin-Ping Han - Fishkill NY, US
Thomas S. Kanarsky - Hopewell Junction NY, US
Hung Y. Ng - New Milford NJ, US
Qiqing Quyang - Yorktown Heights NY, US
Gen Pei - Mahopac NY, US
Chun-Yung Sung - Poughkeepsie NY, US
Henry K. Utomo - Newburgh NY, US
Thomas A. Wallner - Pleasant Valley NY, US
International Classification:
H01L 29/78
H01L 21/336
US Classification:
257351, 438163, 438154, 257E29295, 257E21409
Abstract:
In one embodiment, the invention is a complementary metal-oxide-semiconductor device with an embedded stressor. One embodiment of a field effect transistor includes a silicon on insulator channel, a gate electrode coupled to the silicon on insulator channel, and a stressor embedded in the silicon on insulator channel and spaced laterally from the gate electrode, where the stressor is formed of a silicon germanide alloy whose germanium content gradually increases in one direction.
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Hung Fai Ng from New York, NY, age ~70 Get Report