Resumes
Resumes
Senior Design Engineer
View pageLocation:
Portland, OR
Industry:
Semiconductors
Work:
Intel Corporation
Senior Design Engineer
Cadence Design Systems 1997 - 2001
Consulting Engineer
Senior Design Engineer
Cadence Design Systems 1997 - 2001
Consulting Engineer
Education:
University of Washington 1994 - 1998
Bachelors, Bachelor of Science
Bachelors, Bachelor of Science
Skills:
Asic
Vlsi
Soc
Rtl Design
Timing
Static Timing Analysis
Ic
Semiconductors
Debugging
Verilog
System on A Chip
Vlsi
Soc
Rtl Design
Timing
Static Timing Analysis
Ic
Semiconductors
Debugging
Verilog
System on A Chip