Joo H Lee

20220231698, Jul 21, 2022

Jun 24, 2021

17/357953

- Suwon-si, KR
JOO HWAN LEE - San Jose CA, US
ARMIN HAJ ABOUTALEBI - San Jose CA, US
PRAVEEN KRISHNAMOORTHY - Fremont CA, US
XIAODONG ZHAO - Cupertino CA, US
HUI ZHANG - San Jose CA, US
YANG SEOK KI - Palo Alto CA, US

H03M 7/30
G06F 3/06

An accelerator is disclosed. The accelerator may include a memory that may store a dictionary table. An address generator may be configured to generate an address in the dictionary table based on an encoded value, which may have an encoded width. An output filter may be configured to filter a decoded value from the dictionary table based on the encoded value, the encoded width, and a decoded width of the decoded data. The accelerator may be configured to support at least two different encoded widths.

20220207040, Jun 30, 2022

Feb 11, 2021

17/174350

- Suwon-si, KR
Yiqun ZHANG - Sunnyvale CA, US
Joo Hwan LEE - San Jose CA, US
Yang Seok KI - Palo Alto CA, US
Andrew CHANG - Los Altos CA, US

G06F 16/2453

A method of processing data may include receiving a stream of first keys associated with first data, receiving a stream of second keys associated with second data, comparing, in parallel, a batch of the first keys and a batch of the second keys, collecting one or more results from the comparing, and gathering one or more results from the collecting. The collecting may include reducing an index matrix and a mask matrix. Gathering one or more results may include storing, in a leftover vector, at least a portion of the one or more results from the collecting. Gathering one or more results further may include combining at least a portion of the leftover vector from a first cycle with at least a portion of the one or more results from the collecting from a second cycle.

20210334162, Oct 28, 2021

Jul 2, 2021

17/367315

- Suwon-si, KR
Joo Hwan LEE - San Jose CA, US
Rekha PITCHUMANI - Fairfax CA, US
Yang Seok KI - Palo Alto CA, US

G06F 11/10
G06F 13/28

According to one general aspect, an apparatus may include a host interface circuit configured to receive offloading instructions from a host processing device, wherein the offloading instructions instruct the apparatus to compute an error correction code associated with a plurality of data elements. The apparatus may include a memory interface circuit configured to receive the plurality of data elements. The apparatus may include a plurality of memory buffer circuits configured to temporarily store the plurality of data elements. The apparatus may include a plurality of error code computation circuits configured to, at least in part, compute the error correction code without additional processing by the host processing device.

20210124500, Apr 29, 2021

Mar 17, 2020

16/821811

- Suwon-si, KR
Hui Zhang - San Jose CA, US
Joo Hwan Lee - San Jose CA, US
Yang Seok Ki - Palo Alto CA, US

G06F 3/06

A storage system includes: a storage device to store an array of data elements associated with a sort operation; a storage interface to facilitate communications between the storage device and a host computer; and a reconfigurable processing device communicably connected to the storage device, the reconfigurable processing device including: memory to store input data read from the storage device, the input data corresponding to the array of data elements stored in the storage device; and a kernel including one or more compute components to execute the sort operation on the input data stored in the memory according to a SORT command received from the host computer. The reconfigurable processing device is to dynamically instantiate the one or more compute components to accelerate the sort operation.

20200234115, Jul 23, 2020

Jun 14, 2019

16/442440

- Suwon-si, KR
Joo Hwan LEE - San Jose CA, US
Yang Seok KI - Palo Alto CA, US

G06N 3/08
G06F 9/50
G06N 3/04

Computing resources may be optimally allocated for a multipath neural network using a multipath neural network analyzer that includes an interface and a processing device. The interface receives a multipath neural network. The processing device generates the multipath neural network to include one or more layers of a critical path through the multipath neural network that are allocated a first allocation of computing resources that are available to execute the multipath neural network. The critical path limits throughput of the multipath neural network. The first allocation of computing resources reduces an execution time of the multipath neural network to be less than a baseline execution time of a second allocation of computing resources for the multipath neural network. The first allocation of computing resources for a first layer of the critical path is different than the second allocation of computing resources for the first layer of the critical path.

20200192757, Jun 18, 2020

Feb 8, 2019

16/271777

- Suwon-si, KR
Joo Hwan LEE - San Jose CA, US
Rekha PITCHUMANI - Fairfax CA, US
Yang Seok KI - Palo Alto CA, US

G06F 11/10
G06F 13/28

According to one general aspect, an apparatus may include a host interface circuit configured to receive offloading instructions from a host processing device, wherein the offloading instructions instruct the apparatus to compute an error correction code associated with a plurality of data elements. The apparatus may include a memory interface circuit configured to receive the plurality of data elements. The apparatus may include a plurality of memory buffer circuits configured to temporarily store the plurality of data elements. The apparatus may include a plurality of error code computation circuits configured to, at least in part, compute the error correction code without additional processing by the host processing device.

20200192880, Jun 18, 2020

Feb 12, 2019

16/274232

- Suwon-si, KR
Joo Hwan LEE - San Jose CA, US
Yang Seok KI - Palo Alto CA, US

G06F 16/22
G06F 16/901
G06F 16/28
G06F 16/23
G06F 16/2455

According to one general aspect, an apparatus may include a host processor interface circuit configured to communicate data and commands with an external host processor circuit. The apparatus may include a controller processor circuit configured to merge graph data elements into merged dynamic shards, wherein the merged dynamic shards include the same number of graph data elements. The apparatus may include a non-volatile memory configured to store data in an at least a partial graph structure, wherein the graph structure includes data elements that each include vertexes and an edge, and wherein sub-portions of the data elements are grouped into shards.