Search

Ho V Truong

from Westminster, CA
Age ~57
Get Report
Also known as:
Ho V Pruong, Hai Ho Truong, Ho O Vantruong, Hai H Truong, Hiep V Truong, Hal H Truong, Truong Ho, Ho Hong, Ho G, Anh Truong Hong
Phone and address:
9702 Bolsa Ave, Westminster, CA 92683
(714) 531-4497
Related to:
Judy Du, 39Thanh Hong Nguyen, 66Van T Truong, 75Trang N Than, 50Hue T Truong, 55Vien Chung V Sinh, 50Hung Hoang Cao, 73Anhtuan A Nguyen, 60Mimi Hoai Dinh, 58Thuy DinhTam D Nguyen, 59Luong V Nguyen, 43Xem T NguyenMichael T Truong, 55V LecangVan B Truong, 60Tuan Anh Tran, 54Tinh V Truong, 61Finh ChungTu Q Troung
Connected to:
Amy Truong, 42Andrew K Truong, 29Beckie N Truong, 64Bich L Truong, 62Casie Truong, 37Dalina P Truong, 32De C Truong, 60Diana Truong, 40Doan T Truong, 64Doi T Truong, 57

Ho Truong Phones & Addresses

  • 9702 Bolsa Ave, Westminster, CA 92683 (714) 531-4497
  • San Jose, CA
  • Santa Ana, CA
  • Beaverton, OR

Resumes

Resumes

Ho Truong Photo 1

Thermal

View page
Location:
San Francisco, CA
Industry:
Computer Hardware
Work:
Google
Thermal
Gopro
Mechanical Thermal Technician
Apple Jul 2005 - May 2015
Technician
Terastor 1998 - 2000
Mechanical Technician
Skills:
Testing
Hardware
Troubleshooting
Manufacturing
Electronics
Computer Hardware
Product Development
Failure Analysis
Semiconductors
Product Management
Ilife
Ic
Cross Functional Team Leadership
Engineering
Languages:
English

Publications

Us Patents

Clock Generator With Programmable Non-Overlapping Clock-Edge Capability

View page
US Patent:
6489826, Dec 3, 2002
Filed:
Oct 5, 2001
Appl. No.:
09/970773
Inventors:
Ho Dai Truong - San Jose CA
Chong Ming Lin - Sunnyvale CA
Assignee:
Seiko Epson Corporation - Tokyo
International Classification:
H03K 3037
US Classification:
327259, 327239, 327270
Abstract:
A system and method for generating and optimizing clock signals with non-overlapping edges on a chip using a unique programmable on-chip clock generator. Overlapping of the edges of the clocking signals is avoided by adjusting an amount of delay introduced in the on-chip clock generator circuit. The amount of delay is adjusted by programming the on-chip clock generator using either hardware and/or software programming. In hardware programming, the amount of delay adjusted by physically altering the composition of delay elements in the on-chip clock generator. In software programming, the delay is adjusted using software commands to control the operation of delay elements in the on-chip clock generator, or to select the paths that delay the signals.

Clock Generator With Programmable Non-Overlapping-Clock-Edge Capability

View page
US Patent:
6653881, Nov 25, 2003
Filed:
Oct 23, 2002
Appl. No.:
10/277757
Inventors:
Ho Dai Truong - San Jose CA
Chong Ming Lin - Sunnyvale CA
Assignee:
Seiko Epson Corporation - Tokyo
International Classification:
H03H 1116
US Classification:
327259, 327239, 327295
Abstract:
A system and method for generating and optimizing clock signals with non-overlapping edges on a chip using a unique programmable on-chip clock generator. Overlapping of the edges of the clocking signals is avoided by adjusting an amount of delay introduced in the on-chip clock generator circuit. The amount of delay is adjusted by programming the on-chip clock generator using either hardware and/or software programming. In hardware programming, the amount of delay adjusted by physically altering the composition of delay elements in the on-chip clock generator. In software programming, the delay is adjusted using software commands to control the operation of delay elements in the on-chip clock generator, or to select the paths that delay the signals.

Clock Generator With Programmable Non-Overlapping-Clock-Edge Capability

View page
US Patent:
6900682, May 31, 2005
Filed:
Sep 25, 2003
Appl. No.:
10/669659
Inventors:
Ho Dai Truong - San Jose CA, US
Chong Ming Lin - Sunnyvale CA, US
Assignee:
Seiko Epson Corporation - Tokyo
International Classification:
H03H011/16
H03K005/13
US Classification:
327259, 327239
Abstract:
A system and method for generating and optimizing clock signals with non-overlapping edges on a chip using a unique programmable on-chip clock generator. Overlapping of the edges of the clocking signals is avoided by adjusting an amount of delay introduced in the on-chip clock generator circuit. The amount of delay is adjusted by programming the on-chip clock generator using either hardware and/or software programming. In hardware programming, the amount of delay adjusted by physically altering the composition of delay elements in the on-chip clock generator. In software programming, the delay is adjusted using software commands to control the operation of delay elements in the on-chip clock generator, or to select the paths that delay the signals.

Clock Generator With Programmable Non-Overlapping-Clock-Edge Capability

View page
US Patent:
7352222, Apr 1, 2008
Filed:
Apr 22, 2005
Appl. No.:
11/111799
Inventors:
Ho Dai Truong - San Jose CA, US
Chong Ming Lin - Sunnyvale CA, US
Assignee:
Seiko Epson Corporation
International Classification:
H03K 5/13
US Classification:
327259, 327239, 327270
Abstract:
A system and method for generating and optimizing clock signals with non-overlapping edges on a chip using a unique programmable on-chip clock generator. Overlapping of the edges of the clocking signals is avoided by adjusting an amount of delay introduced in the on-chip clock generator circuit. The amount of delay is adjusted by programming the on-chip clock generator using either hardware and/or software programming. In hardware programming, the amount of delay adjusted by physically altering the composition of delay elements in the on-chip clock generator. In software programming, the delay is adjusted using software commands to control the operation of delay elements in the on-chip clock generator, or to select the paths that delay the signals.

Clock Generator With Programmable Non-Overlapping-Clock-Edge Capability

View page
US Patent:
7642832, Jan 5, 2010
Filed:
Jan 22, 2008
Appl. No.:
12/017849
Inventors:
Ho Dai Truong - San Jose CA, US
Chong Ming Lin - Sunnyvale CA, US
Assignee:
Seiko Epson Corporation - Tokyo
International Classification:
H03H 11/16
H03K 5/13
US Classification:
327259, 327239
Abstract:
A system and method for generating and optimizing clock signals with non-overlapping edges on a chip using a unique programmable on-chip clock generator. Overlapping of the edges of the clocking signals is avoided by adjusting an amount of delay introduced in the on-chip clock generator circuit. The amount of delay is adjusted by programming the on-chip clock generator using either hardware and/or software programming. In hardware programming, the amount of delay adjusted by physically altering the composition of delay elements in the on-chip clock generator. In software programming, the delay is adjusted using software commands to control the operation of delay elements in the on-chip clock generator, or to select the paths that delay the signals.

Layout Design Of Integrated Circuit, Especially Datapath Circuitry, Using Function Cells Formed With Fixed Basic Cell And Configurable Interconnect Networks

View page
US Patent:
60319828, Feb 29, 2000
Filed:
Nov 15, 1996
Appl. No.:
8/749861
Inventors:
Ho D. Truong - San Jose CA
DongWon Park - Santa Clara CA
Hyungsuk Yang - Cupertino CA
Seokkyun Jung - San Jose CA
Assignee:
Samsung Electronics Co., Ltd. - Kyungki-do
International Classification:
G06F 1750
H01L 2710
US Classification:
39550017
Abstract:
A group of function cells (e. g. , 40), each created from one or more implementations of a fixed basic cell (20), are utilized in designing a layout for at least part of an integrated circuit. Each basic cell implementation contains a plurality of unconnected transistors (Q1-Q10) arranged in a transistor pattern identical to, or a mirror image of, the transistor pattern in each other basic cell implementation. Transistors of a specified polarity type in each basic cell implementation are normally of two or more different current-carrying capabilities. Each function cell has an interconnection network (42-44) for electrically interconnecting transistors in that function cell to perform a specified electronic function. The function cells typically form a cell library from which certain function cells are selected for generating the layout. The present layout technique is particularly applicable to laying out datapath circuitry (90) in an integrated circuit.

Integrated Circuit With Hardware-Based Programmable Non-Overlapping-Clock-Edge Capability

View page
US Patent:
61631949, Dec 19, 2000
Filed:
Aug 17, 1999
Appl. No.:
9/376186
Inventors:
Ho Dai Truong - San Jose CA
Chong Ming Lin - Sunnyvale CA
Assignee:
Seiko Epson Corporation - Tokyo
International Classification:
H03K 3037
US Classification:
327259
Abstract:
A system and method for generating and optimizing clock signals with non-overlapping edges on a chip using a unique programmable on-chip clock generator. Overlapping of the edges of the clocking signals is avoided by adjusting an amount of delay introduced in the on-chip clock generator circuit. The amount of delay is adjusted by programming the on-chip clock generator using either hardware and/or software programming. In hardware programming, the amount of delay adjusted by physically altering the composition of delay elements in the on-chip clock generator. In software programming, the delay is adjusted using software commands to control the operation of delay elements in the on-chip clock generator, or to select the paths that delay the signals.

Clock Generator With Programmable Non-Overlapping Clock Edge Capability

View page
US Patent:
54444055, Aug 22, 1995
Filed:
Jun 8, 1994
Appl. No.:
8/255910
Inventors:
Ho D. Truong - San Jose CA
Chong M. Lin - Sunnyvale CA
Assignee:
Seiko Epson Corporation - Tokyo
International Classification:
H03K 3037
US Classification:
327239
Abstract:
A system and method for generating and optimizing clock signals with non-overlapping edges on a chip using a unique programmable on-chip clock generator. Overlapping of the edges of the clocking signals is avoided by adjusting an amount of delay introduced in the on-chip clock generator circuit. The amount of delay is adjusted by programming the on-chip clock generator using either hardware and/or software programming. In hardware programming, the amount of delay adjusted by physically altering the composition of delay elements in the on-chip clock generator. In software programming, the delay is adjusted using software commands to control the operation of delay elements in the on-chip clock generator, or to select the paths that delay the signals.
Control profile
Ho V Truong from Westminster, CA, age ~57 Get Report