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Hieu Q Lam

from Fairfield, CA
Age ~68
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Also known as:
Hieu Quang Lam, Hieu O Lam
Phone and address:
2478 Atlantic Ave, Fairfield, CA 94533
(707) 426-6586
Related to:
Kathleen H Lam, 61Liem LamLan LamJoanne Lam, 92Susan LamLam Cung
Connected to:
Abdoulaye Lam, 42Adeline Lam, 46Alisa L Lam, 65Amethyst Lam, 56Angelica M Lam, 57Anna M Lam, 68Awilda O Lam, 54Beatrice M Lam, 76Belle B Lam, 76Blaine C Lam, 31

Hieu Lam Phones & Addresses

  • 2478 Atlantic Ave, Fairfield, CA 94533 (707) 426-6586
  • San Francisco, CA

Work

Company: Fine pitch technology inc Address: 44300 Christy St, Fremont, CA 94538 Phones: (510) 668-8300 Position: Production manager Industries: Business Services

Resumes

Resumes

Hieu Lam Photo 1

Senior Dev Engineer At Hgst

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Position:
Senior Dev Engineer at HGST, a Western Digital company
Location:
Milpitas, California
Industry:
Semiconductors
Work:
HGST, a Western Digital company since Dec 2009
Senior Dev Engineer
Seagate Technology - Fremont Dec 2006 - Dec 2009
Senior RMO Dev Engineer
IBM 1998 - 2003
Advisory Engineer
Education:
University of Washington
Hieu Lam Photo 2

Hieu Lam

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Location:
San Francisco Bay Area
Industry:
Financial Services

Business Records

Name / Title
Company / Classification
Phones & Addresses
Hieu Lam
Production Manager
Fine Pitch Technology Inc
Business Services
44300 Christy St, Fremont, CA 94538

Publications

Us Patents

Controlling The Thickness Of Wafers During The Electroplating Process

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US Patent:
7914657, Mar 29, 2011
Filed:
Dec 1, 2005
Appl. No.:
11/292606
Inventors:
Wai B. Fu - Menlo Park CA, US
Hieu Lam - Milpitas CA, US
Shahram Y. Mehdizadeh - Valley Village CA, US
Yeak-Chong Wong - San Jose CA, US
Assignee:
Hitachi Global Storage Technologies, Netherlands B.V. - Amsterdam
International Classification:
C25D 21/12
US Classification:
205 84, 2042287
Abstract:
Embodiments of the present invention pertain to controlling thickness of wafers during electroplating process. Information pertaining to an old current used during an electroplating process of a previous wafer is received. Information pertaining to the thickness of the previous wafer is received. A new current is automatically determined. The new current is to be used during an electroplating process for a new wafer. The new current is determined based on the information pertaining to the old current and the information pertaining to the thickness of the previous wafer.

Method To Protect Magnetic Bits During Planarization

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US Patent:
20130001188, Jan 3, 2013
Filed:
Jun 30, 2011
Appl. No.:
13/174321
Inventors:
David Kuo - Palo Alto CA, US
Michael R. Feldbaum - San Jose CA, US
Paritosh Rajora - Santa Clara CA, US
Hieu Lam - Milpitas CA, US
Assignee:
SEAGATE TECHNOLOGY, LLC - Cupertino CA
International Classification:
G11B 5/84
B05C 9/06
B32B 3/28
B05D 3/00
C23F 1/00
C23F 1/08
B05D 1/36
US Classification:
216 22, 1563451, 428174
Abstract:
The embodiments disclose a method to protect magnetic bits during carbon field planarization, including depositing a stop layer upon magnetic bits and magnetic film of a patterned stack, depositing a carbon fill layer on the stop layer and using the stop layer during planarization and etch-back of the carbon field to protect the patterned stack magnetic bits during the carbon field planarization.
Control profile
Hieu Q Lam from Fairfield, CA, age ~68 Get Report