Hiep H Pham

20200403621, Dec 24, 2020

Sep 2, 2020

17/010322

- Gyeonggi-do, KR
Chih-Wei YAO - Sunnyvale CA, US
Hiep PHAM - San Jose CA, US

H03L 7/087
H04L 27/227
H03L 7/08
H03L 7/10

A synchronized I/Q detection circuit is provided. A first subset of input signals and, subsequently, a second subset of input signals are provided by a first multiplexer and received by a first phase detector. Outputs of the first phase detector are receiving, by a first reset and sampling circuit. A second set of input signals are provided by a second multiplexer and received by a second phase detector, from a second multiplexer, while the first multiplexer receives the first and second subsets of input signals. The first subset of input signals has a same phase order as the second set of input signals, and the second subset of input signals has a different phase order than the second set of input signals. Outputs of the second phase detector are received by a second reset and sampling circuit. A comparator outputs a detected phase difference based on the outputs of the first and second reset and sampling circuits.

20200099380, Mar 26, 2020

Dec 14, 2018

16/220898

- Gyeonggi-do, KR
Chih-Wei YAO - Sunnyvale CA, US
Hiep PHAM - San Jose CA, US

H03L 7/087
H03L 7/10
H03L 7/08
H04L 27/227

A synchronized in-phase/quadrature phase (I/Q) detection circuit and a method of the same are provided. The synchronized I/Q detection circuit includes a first logic circuit; a first filter; a first reset and sampling circuit; a first multiplexer; a second logic circuit; a second filter; a second reset and sampling circuit; a signal generator; and a comparator.

20150207648, Jul 23, 2015

Feb 10, 2014

14/176728

- San Jose CA, US
Tomasz Prokop - Pleasanton CA, US
Hiep T. Pham - San Jose CA, US
Volodymyr Shvydun - Los Altos CA, US
Adam B. Healey - Newburyport MA, US

LSI Corporation - San Jose CA

H04L 25/03
H04L 27/00
H04L 7/00

Modular, low power serializer-deserializer receivers and methods for configuring such receivers are disclosed. The disclosed receivers are configured to sample input signals at the front-end utilizing a plurality of track-and-hold circuits time-interleaved based on a plurality of phase-shifted clock signals. The disclosed receivers are also modular and various processing components, including analog front-end and equalizers, are selectively utilized based on the determined length of the communication channel, ranging from ultra short reach applications to very short reach, medium reach, long reach and extra long reach applications.