Hao L Chen

7836372, Nov 16, 2010

Jun 8, 2007

11/760566

Luka Bodrozic - San Francisco CA, US
Sukalpa Biswas - Fremont CA, US
Hao Chen - San Ramon CA, US
Sridhar P. Subramanian - Cupertino CA, US
James B. Keller - Redwood City CA, US

Apple Inc. - Cupertino CA

G01R 31/28
G11C 29/00

714743, 714718

In one embodiment, an apparatus comprises an interconnect; at least one processor coupled to the interconnect; and at least one memory controller coupled to the interconnect. The memory controller is programmable by the processor into a loopback test mode of operation and, in the loopback test mode, the memory controller is configured to receive a first write operation from the processor over the interconnect. The memory controller is configured to route write data from the first write operation through a plurality of drivers and receivers connected to a plurality of data pins that are capable of connection to one or more memory modules. The memory controller is further configured to return the write data as read data on the interconnect for a first read operation received from the processor on the interconnect.

8055975, Nov 8, 2011

Jun 5, 2007

11/758322

Brian P. Lilly - San Francisco CA, US
Robert Gries - Woodstock CT, US
Sridhar P. Subramanian - Cupertino CA, US
Sukalpa Biswas - Fremont CA, US
Hao Chen - San Ramon CA, US

Apple Inc. - Cupertino CA

H03M 13/00

714758, 714784, 714785

In one embodiment, an apparatus includes a check/correct circuit coupled to a control circuit. The check/correct circuit is coupled to receive a block of data and corresponding check bits. The block of data is received as N transmissions, each transmission including M data bits and L check bits. The check/correct circuit is configured to detect one or more errors in each of a plurality of non-overlapping windows of K bits in the M data bits, responsive to the M data bits and the L check bits. The control circuit is configured to record which of the plurality of windows have had errors detected and, if a given window of the plurality of windows has had errors detected in each of the N transmissions of the block, the control circuit is configured to signal a device failure. Each of K, L, M, and N are integers greater than one.

8086915, Dec 27, 2011

Oct 21, 2010

12/909073

Luka Bodrozic - San Francisco CA, US
Sukalpa Biswas - Fremont CA, US
Hao Chen - San Ramon CA, US
Sridhar P. Subramanian - Cupertino CA, US
James B. Keller - Redwood City CA, US

Apple Inc. - Cupertino CA

G01R 31/28
G11C 29/00
G06F 11/00

714716, 714719, 714743

In one embodiment, an apparatus comprises an interconnect; at least one processor coupled to the interconnect; and at least one memory controller coupled to the interconnect. The memory controller is programmable by the processor into a loopback test mode of operation and, in the loopback test mode, the memory controller is configured to receive a first write operation from the processor over the interconnect. The memory controller is configured to route write data from the first write operation through a plurality of drivers and receivers connected to a plurality of data pins that are capable of connection to one or more memory modules. The memory controller is further configured to return the write data as read data on the interconnect for a first read operation received from the processor on the interconnect.

8219880, Jul 10, 2012

Sep 27, 2011

13/246736

Brian P. Lilly - San Francisco CA, US
Robert Gries - Woodstock CT, US
Sridhar P. Subramanian - Cupertino CA, US
Sukalpa Biswas - Fremont CA, US
Hao Chen - San Ramon CA, US

Apple Inc. - Cupertino CA

H03M 13/00

714758, 714784, 714785

In one embodiment, an apparatus includes a check/correct circuit coupled to a control circuit. The check/correct circuit is coupled to receive a block of data and corresponding check bits. The block of data is received as N transmissions, each transmission including M data bits and L check bits. The check/correct circuit is configured to detect one or more errors in each of a plurality of non-overlapping windows of K bits in the M data bits, responsive to the M data bits and the L check bits. The control circuit is configured to record which of the plurality of windows have had errors detected and, if a given window of the plurality of windows has had errors detected in each of the N transmissions of the block, the control circuit is configured to signal a device failure. Each of K, L, M, and N are integers greater than one.

8301941, Oct 30, 2012

Nov 28, 2011

13/305202

Luka Bodrozic - San Francisco CA, US
Sukalpa Biswas - Fremont CA, US
Hao Chen - San Ramon CA, US
Sridhar P. Subramanian - Cupertino CA, US
James B. Keller - Redwood City CA, US

Apple Inc. - Cupertino CA

G01R 31/28
G11C 29/00
G06F 11/00

714716, 714718, 714743

An apparatus may include an interconnect; at least one processor coupled to the interconnect; and at least one memory controller coupled to the interconnect. The memory controller may be programmable by the processor into a loopback test mode of operation and, in the loopback test mode, the memory controller may be configured to receive a first write operation from the processor over the interconnect. The memory controller may be configured to route write data from the first write operation through a plurality of drivers and receivers connected to a plurality of data pins that are capable of connection to one or more memory modules. The memory controller may be further configured to return the write data as read data on the interconnect for a first read operation received from the processor on the interconnect.

8314807, Nov 20, 2012

Sep 16, 2010

12/883864

Sukalpa Biswas - Fremont CA, US
Hao Chen - San Ramon CA, US

Apple Inc. - Cupertino CA

G09G 5/39

345531

In an embodiment, a memory controller includes multiple ports. Each port may be dedicated to a different type of traffic. In an embodiment, quality of service (QoS) parameters may be defined for the traffic types, and different traffic types may have different QoS parameter definitions. The memory controller may be configured to schedule operations received on the different ports based on the QoS parameters. In an embodiment, the memory controller may support upgrade of the QoS parameters when subsequent operations are received that have higher QoS parameters, via sideband request, and/or via aging of operations. In an embodiment, the memory controller is configured to reduce emphasis on QoS parameters and increase emphasis on memory bandwidth optimization as operations flow through the memory controller pipeline.

8357618, Jan 22, 2013

Oct 24, 2008

12/257953

Christopher Dennis Bencher - San Jose CA, US
Huixiong Dai - San Jose CA, US
Li Yan Miao - San Francisco CA, US
Hao Chen - Santa Clara CA, US

Applied Materials, Inc. - Santa Clara CA

H01L 21/31

438763, 438689, 438703, 257313, 257E2124

A method for doubling the frequency of a lithographic process using a photo-resist template mask is described. A device layer having a photo-resist layer formed thereon is first provided. The photo-resist layer is patterned to form a photo-resist template mask. A spacer-forming material layer is deposited over the photo-resist template mask. The spacer-forming material layer is etched to form a spacer mask and to expose the photo-resist template mask. The photo-resist template mask is then removed and an image of the spacer mask is finally transferred to the device layer.

8374833, Feb 12, 2013

Jun 14, 2010

12/815112

Hao Chen - Pleasanton CA, US
Jingxiao Xu - Dublin CA, US
Chi-Hsien Wang - Pleasanton CA, US

Livermore Software Technology Corporation - Livermore CA

G06G 7/48

703 6

Hybrid elements that enable coupling effects between SPH particles and FEM solid are disclosed. According to one aspect of the present invention, hybrid elements are configured to facilitate coupling effect of solid element based on finite element method (FEM) and one or more corresponding particles based on smoothed particle hydrodynamics (SPH). Hybrid elements are defined in a computer aided engineering (CAE) grid model as a buffer or interface between the SPH particles and FEM solids. For example, a portion of the grid model comprises SPH particles because the likelihood of enduring large deformation, while the rest of the model comprises FEM solid elements. Hybrid elements are placed between the solids and the particles. Each hybrid element comprises two layers: solid layer and particle layer.