Han Y Koh

58780530, Mar 2, 1999

Jun 9, 1997

8/871086

Han Young Koh - Fremont CA
Tak K. Young - Cupertino CA
Chiping Ju - Saratoga CA
Hurley H. Song - San Jose CA

Synopsys, Inc. - Mountain View CA

G06F 1100

371 221

The present invention pertains to a method for analyzing a semiconductor chip design for determining potential voltage drop and electromigration problems. Initially, the semiconductor chip design is divided into a plurality of blocks. A block level verification is then performed based on the assumption that full voltage is being supplied to each of the blocks. Next, the blocks are modeled by an equivalent RC network. This RC network is then reduced into a simpler representation. The voltage drops are determined based on the reduced, equivalent model. The blocks are then reanalyzed with the supply voltage input to the blocks reduced according to the calculated voltage drops. Thereby, a more realistic simulation can be achieved.

62498983, Jun 19, 2001

Jun 30, 1998

9/109999

Han Young Koh - Fremont CA
Tak K. Young - Cupertino CA

Synopsys, Inc. - Mountain View CA

G06F 1750

716 4

A unique, efficient method and system for reliability simulation of a semiconductor chip design comprising millions of transistors. Specifically, the instant method starts by storing device information about a chip design as inputted. Next, by first partitioning the complex circuit of the design into numerous smaller stages, each of which confines direct current flow within its boundary, then estimating the current consumption and the relative current contribution of each transistor for each stage, the method of the present invention determines the individual currents of all power network transistors with sufficient accuracy for reliability simulation. The instant method then uses the individual transistor currents and the stored device information, including data of an accurate resistor-capacitor model of the power network, to determine the branch currents and node voltages in all interconnect wires of the power network. Finally, the instant method reports all potential problems of the design identified based on the values of the branch currents and node voltages. As such, the present invention enables circuit designers to pinpoint where voltage drop and electro-migration may pose problems and take appropriate corrective actions before chips are fabricated and sold.

59333588, Aug 3, 1999

Sep 30, 1997

8/940627

Han Young Koh - Fremont CA
Tak K. Young - Cupertino CA

Synopsys, Inc. - Mountain View CA

G06F 1750
G06F 1760
G06F 1900

364578

A method for testing for power supply network voltage drop violations in an integrated circuit through a computer simulation. First, the IC chip area is divided into a number of discrete regions. The simulation time is divided into a number of time segments. Next, the average aggregate currents corresponding to the transistors for each of the regions are calculated for each of the time segments. Only when a peak average current occurs for any one of the plurality of regions is the power supply network of the IC chip simulated for that time segment. Based on the voltage drops as determined by the power network simulation, violation conditions can be easily identified. Thus, the power network of the IC chip is simulated only when there is found to be high switching activity in some region of the chip. This is more efficient than performing power network voltage drop analyses all the time, even when switching activity throughout the chip is low and the likelihood of any voltage drop violations is very low.