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Guang Chen

from San Francisco, CA
Age ~68
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Also known as:
Guan G Chen
Phone and address:
2955 26Th St APT B, San Francisco, CA 94110
Related to:
Ming Chen Yu, 41Weilin ChenGuiying Zhang, 71Kevin L Chen, 41Mari Chen, 42Qiren Chen, 89Qiren ChenCharles J Zhang, 67Hui Chen, 63Y U ChenSanjun R Chun, 50Guangqun Chen, 57Charles Zhang
Connected to:
Ai S Chen, 71Ai Chen, 70Alfred C Chen, 53Alix Y Chen, 33Aloysius J Chen, 93Amie K Chen, 63Amily M Chen, 35Andersen Y Chen, 32Angela B Chen, 44Angeline Chen, 48

Guang Chen Phones & Addresses

  • 2955 26Th St APT B, San Francisco, CA 94110

Resumes

Resumes

Guang Chen Photo 1

Software Engineer At Broadcom

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Location:
San Francisco Bay Area
Industry:
Consumer Electronics
Guang Chen Photo 2

Engineer

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Location:
San Francisco, CA
Industry:
Computer Software
Work:
Microsoft
Engineer
Guang Chen Photo 3

Member Of Technical Staff, Signal Integrity

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Location:
San Francisco, CA
Industry:
Electrical/Electronic Manufacturing
Work:
Altera
Member of Technical Staff, Signal Integrity
Formfactor Inc. Oct 2006 - Oct 2008
Signal Integrity Engineer
Education:
University of Arizona 2001 - 2006
Doctorates, Doctor of Philosophy Nankai University
Guang Chen Photo 4

Guang Chen

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Guang Chen Photo 5

Application Architec At First Data Corporation

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Location:
United States
Industry:
Financial Services
Guang Chen Photo 6

Guang Chen

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Location:
United States

Business Records

Name / Title
Company / Classification
Phones & Addresses
Guang Jin Chen
President
HONG TUO STONE PRODUCTS, INC
Whol Brick/Stone Material
237 10 St, Oakland, CA 94607
2493 Washington Ave, San Leandro, CA 94577
1355 Pearson Ave, San Leandro, CA 94577
Guang Long Chen
Yoppi Yogurt LLC
Trademark Owner · Whol Dairy Products
1815 Ygnacio Vly Rd, Walnut Creek, CA 94598
7836 Pineville Cir, Hayward, CA 94552
Guang Wu Chen
President
PING YUEN RESIDENTS IMPROVEMENT ASSOCIATION
Civic/Social Association
799 Pacific Ave, San Francisco, CA 94133
(415) 781-2860
Guang Qin Chen
President
NEW ART STONES INC
1257 Terra Ave, San Leandro, CA 94578

Publications

Us Patents

Dynamic Power Load Line By Configuration

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US Patent:
20220335190, Oct 20, 2022
Filed:
Jul 1, 2022
Appl. No.:
17/856776
Inventors:
Guang Chen - Fremont CA, US
Yuet Li - Fremont CA, US
Archanna Srinivasan - San Jose CA, US
International Classification:
G06F 30/347
Abstract:
Systems or methods of the present disclosure may provide for determining a load line for operation of a programmable logic fabric where the load line is based at least in part on design configuration details for a design or a configuration rather for generic deployment of the programmable logic device. The load line may be determined using software modeling for the design or configuration. Additionally or alternatively, the load line may be determined using runtime testing and sensing of real-world parameters. This determination based on real-world parameters of a deployment of the configuration or design is based on a determination of a step load for the design or configuration.

Circuits And Methods For Detecting Decreases In A Supply Voltage In An Integrated Circuit

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US Patent:
20210313989, Oct 7, 2021
Filed:
Jun 21, 2021
Appl. No.:
17/353549
Inventors:
- Santa Clara CA, US
Guang Chen - Fremont CA, US
Venu Kondapalli - San Jose CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H03K 19/1778
H03K 21/08
Abstract:
An integrated circuit includes a first voltage decrease detection circuit that has a first comparator circuit that compares a supply voltage in the integrated circuit to a threshold voltage to generate a first detection signal that indicates a decrease in the supply voltage, and a first timestamp storage circuit that stores a first timestamp in response to the first detection signal indicating the decrease. The integrated circuit includes a second voltage decrease detection circuit that has a second comparator circuit that compares the supply voltage to the threshold voltage to generate a second detection signal that indicates the decrease, and a second timestamp storage circuit that stores a second timestamp in response to the second detection signal indicating the decrease. The integrated circuit includes a control circuit that determines a location of a source of the decrease in the integrated circuit based on the first and the second timestamps.

Interleaving Scheme For Increasing Operating Efficiency During High Current Events On An Integrated Circuit

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US Patent:
20190044514, Feb 7, 2019
Filed:
Dec 22, 2017
Appl. No.:
15/852814
Inventors:
- Santa Clara CA, US
Guang Chen - Fremont CA, US
Jun Pin Tan - Kepong, MY
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H03K 19/003
H03K 19/177
H03K 19/00
Abstract:
An integrated circuit configured to execute multiple operations in parallel is provided. The integrated circuit may be organized into multiple logic sectors. Two or more groups of logic sectors may be executed in an interleaved fashion, where successive groups of logic sectors are activated after a predetermined amount of delay. The integrated circuit may include an array of memory cells. Rows of the memory cells may be accessed in an interleaving manner, where successive rows of memory cells are selected after a predetermined amount of delay. Operating groups of circuit components using an interleaving scheme can help improve operational efficiency while reducing power supply noise without having to increase die area for on-die decoupling capacitance.
Control profile
Guang Chen from San Francisco, CA, age ~68 Get Report