Grace Helen Sun

6930362, Aug 16, 2005

Oct 30, 2003

10/698167

Mohammad R. Mirabedini - Redwood City CA, US
Grace S. Sun - Sunnyvale CA, US
Sheldon Aronowitz - San Jose CA, US

LSI Logic Corporation - Milpitas CA

H01L029/76
H01L021/336

257412, 257607, 438197, 438585

A calcium doped polysilicon gate electrodes for PMOS containing semiconductor devices. The calcium doped PMOS gate electrodes reduce migration of the boron dopant out of the gate electrode, through the gate dielectric and into the substrate thereby reducing the boron penetration problem increasingly encountered with smaller device size regimes and their thinner gate dielectrics. Calcium doping of the gate electrode may be achieved by a variety of techniques. It is further believed that the calcium doping may improve the boron dopant activation in the gate electrode, thereby further improving performance.

6989565, Jan 24, 2006

Oct 31, 2003

10/698169

Sheldon Aronowitz - San Jose CA, US
Vladimir Zubkov - Mountain View CA, US
Grace S. Sun - Mountain View CA, US

LSI Logic Corporation - Milpitas CA

H01L 29/792

257324, 257325

An improved semiconductor memory structure and methods for its fabrication are disclosed. The memory structure includes a semiconductor substrate having a dielectric stack formed over a channel region of a semiconductor substrate. The dielectric stack includes a layer of electron trapping material that operates as a charge storage center for memory devices. A gate electrode is connected with the top of the dielectric stack. In various embodiments the electron trapping material forms a greater or lesser portion of the dielectric stack. The invention includes a method embodiment for forming such a memory device.

6998343, Feb 14, 2006

Nov 24, 2003

10/721971

Grace Sun - Mountain View CA, US
Vladimir Zubkov - Mountain View CA, US
William K. Barth - Gresham OR, US
Sethuraman Lakshminarayanan - San Jose CA, US
Agajan Suvkhanov - Portland OR, US
Hao Cui - West Linn OR, US

LSI Logic Corporation - Milpitas CA

H01L 21/44

438659, 438643, 438653, 438677, 257762

A method for forming damascene interconnect copper diffusion barrier layers includes implanting calcium into the sidewalls of the trenches and vias. The calcium implantation into dielectric layers, such as oxides, is used to prevent Cu diffusion into oxide, such as during an annealing process step. The improved barrier layers of the present invention help prevent delamination of the Cu from the dielectric.

7132336, Nov 7, 2006

Apr 15, 2002

10/123263

Sheldon Aronowitz - San Jose CA, US
Vladimir Zubkov - Mountain View CA, US
Grace S. Sun - Mountain View CA, US

LSI Logic Corporation - Milpitas CA

H01L 21/336

438288, 438216, 438287, 257E29309, 257E2118, 257E21679

An improved semiconductor memory structure and methods for its fabrication are disclosed. The memory structure includes a semiconductor substrate having a dielectric region formed over a channel region. A doped region is formed between a top portion and a bottom portion of the dielectric region. This doped region includes a suitable electron affinity material. A gate electrode is connected with the top of the dielectric region. In some embodiments, suitable electron affinity materials are introduced into the doped region using implantation techniques. In another embodiment, the electron affinity material is introduced into the doped region using plasma treatment of the dielectric region and the redeposition of additional dielectric material on top of the dielectric region and doped region.

20040089887, May 13, 2004

Aug 19, 2003

10/643687

Sheldon Aronowitz - San Jose CA, US
Vladimir Zubkov - Mountain View CA, US
Grace Sun - Mountain View CA, US

LSI Logic Corporation - Milpitas CA

H01L029/76

257/288000, 438/585000

A new relatively high-k gate dielectric gate material comprising calcium oxide will reduce leakage from the silicon substrate to the polysilicon gate, prevent boron penetration in p-channel devices, and reduce electron trapping in the dielectric. The surface of a silicon wafer is saturated with hydroxyl groups. A calcium halide, preferably calcium bromide, is heated to a temperature sufficient to achieve atomic layer deposition, and is transported to the silicon wafer. The calcium halide reacts with the hydroxyl groups. Water is added to carry away the resultant hydrogen halide. Gaseous calcium and water are then added to form a calcium oxide gate dielectric, until the desired thickness has been achieved. In an alternative embodiment of the method, the calcium halide is transported to the silicon wafer to react with the hydroxyl groups, followed by transport of gaseous water to the silicon wafer. These two steps are repeated until the desired thickness has been achieved.

20040121550, Jun 24, 2004

Dec 19, 2002

10/325373

Vladimir Zubkov - Mountain View CA, US
Grace Sun - Sunnyvale CA, US
Sheldon Aronowitz - San Jose CA, US

H01L021/336
H01L021/31
H01L021/469

438/287000, 438/785000

A method of creating a barrier to metal contamination in interconnect and gate oxides comprises ion implantation of an alkaline earth metal into the silicon dioxide. The presence of the implanted alkaline earth metal, preferably calcium, traps metal contaminants and thereby creates a barrier to further contamination. Alternatively, the alkaline earth metal can be implanted into the silicon dioxide as a low energy plasma. The implantation of atomic calcium into gate oxide serves to trap boron and thereby minimize boron diffusion from a polysilicon gate into silicon.

20050258475, Nov 24, 2005

Jul 25, 2005

11/189625

Sheldon Aronowitz - San Jose CA, US
Vladimir Zubkov - Mountain View CA, US
Grace Sun - Mountain View CA, US

H01L021/336

257324000

An improved semiconductor memory structure and methods for its fabrication are disclosed. The memory structure includes a semiconductor substrate having a dielectric stack formed over a channel region of a semiconductor substrate. The dielectric stack includes a layer of electron trapping material that operates as a charge storage center for memory devices. A gate electrode is connected with the top of the dielectric stack. In various embodiments the electron trapping material forms a greater or lesser portion of the dielectric stack. The invention includes a method embodiment for forming such a memory device.