Frank Wu

7073952, Jul 11, 2006

Jun 5, 2002

10/163405

Frank Xi Wu - Fremont CA, US
Jian Xu - Pleasanton CA, US
Ming Li - Pleasanton CA, US
Song Peng - Pleasanton CA, US

Avanex Corporation - Fremont CA

G02B 6/26
G02B 7/00

385 62, 385 90, 385 28, 359896, 24828831

An optical alignment device holds fiber collimators in place with extremely good mechanical and environmental stability. The device includes a ball with a hole traversing the ball, an upper clamping block with a first inner concave spherical surface and a lower clamping block with a second inner concave spherical surface. The hole includes a shape that can accommodate or contact an optical component whose alignment is to be controlled. The ball, together with the enclosed optical component is firmly held between the first and second inner concave surfaces of the clamping blocks, which are tightened against the ball with screws. When firmly clamped within the concave surfaces, the ball is prevented from accidental movement but can still rotate about any axis to align the optical component. Once alignment is achieved, the optical component and the ball are secured in place by epoxy, glue, solder or other suitable adhesive.

7440156, Oct 21, 2008

Dec 5, 2005

11/294896

Chun He - Frement CA, US
Frank Xi Wu - Fremont CA, US
River Yang - Guang Dong, CN

Alliance Fiber Optic Products, Inc. - Sunnyvale CA

G02B 26/02

359227

Designs of optical devices for attenuating a light signal are disclosed. According to embodiment, an attenuator includes a screw and a light blocker, wherein the light blocker has only translational movements when the screw is screwed in or out. To facilitate the light signal in and out, a first collimator to receive a light beam, and a second collimator to output the light beam, wherein the light beam is attenuated by the light blocker when the light is transmitted from the first collimator to the second collimator.

8538210, Sep 17, 2013

Jun 29, 2009

12/493855

Daoyi Wang - Sunnyvale CA, US
Frank Wu - Fremont CA, US

Alliance Fiber Optic Products, Inc. - Sunnyvale CA

G02B 6/34
G02B 6/32

385 36, 385 15, 385 16, 385 17, 385 18, 385 20, 385 22, 385 31, 385 33, 385 34, 385 39, 385 47, 385 50

Techniques for designing optical devices that can be manufactured in volume are disclosed. In an exemplary an optical assembly, to ensure that all collimators are on one side to facilitate efficient packaging, all collimators are positioned on both sides of a substrate. Thus one or more beam folding components are used to fold a light beam up and down through the collimators on top of the substrate and bottom of the substrate.

7262904, Aug 28, 2007

Dec 15, 2003

10/736008

Chun He - Fremont CA, US
Frank Wu - Fremont CA, US
Christine Luochanghong Lee - Sunnyvale CA, US
Yao Li - Fremont CA, US
Wei-Shin Tsay - Saratoga CA, US

Alliance Fiber Optic Products, Inc. - Sunnyvale CA

H01S 3/00
G02B 6/42
H04J 14/02

3593372, 385 18, 398 82, 398 85

Improved designs of optical devices for processing optical signals with one or more specified wavelengths are disclosed. According to embodiment, a filter mirror assembly appears an “L” shape and provides a filtering function as well as a reflecting function. The filter mirror assembly is so mounted that a rotation thereof will not alter the optical path the beam positions of signals resulted from a rotation of the filter mirror assembly. To cancel or minimize a lateral shift introduced to a light beam going through an optical filter, an optical compensator is introduced and rotates oppositely whenever the optical filter rotates.

58250840, Oct 20, 1998

Feb 11, 1997

8/795478

John H. Lau - Palo Alto CA
Yung Shih Chen - San Jose CA
Tai-Yu Chou - Pleasanto CA
Frank H. Wu - Sunnyvale CA
Kuan Luen Chen - San Jose CA
Wei H. Koh - Irvine CA

Express Packaging Systems, Inc. - Palo Alto CA

H01L 2312
H01L 2350
H01L 2328

257700

The present invention discloses a new substrate with two metal layer circuit structure and layout for semiconductor packaging. The speed and performance characteristics of the semiconductor device are optimized while the packaging structure is simplified by utilizing only one dielectric layer and conventional printed circuit board fabrication process. The difficulties encountered due to the complexities and higher cost of production required for the multiple layer and high density configuration are thus avoided. The improved circuit structure is achieved by implementing a segmented ring on one side of a substrate and a split plane on the other side thus forming a single layer substrate structure. The edges of the substrate are coated with metal layer to provide inter-layer connections. In addition to the benefits of high performance, low cost, the improved circuit structure and package layout provide flexibility allowing higher degree of freedom for selecting the location and number of input and output signal lines and connections to the ground and power planes from the semiconductor device.

61483885, Nov 14, 2000

Jan 15, 1998

9/007621

Frank Yuhhaw Wu - Fremont CA
Steven K. Feng - Cupertino CA

Seagate Technology, Inc. - Scotts Valley CA

G06F 1206

711217

The present disclosure concerns a method and apparatus for accessing a memory device, such as a dynamic random access memory (DRAM). The DRAM has a plurality of rows, wherein each row has a plurality of DRAM paragraphs comprised of a plurality of contiguous columns. A linear shift register (LSR) translates a plurality of logical addresses to corresponding physical address locations in the DRAM. Each translated physical address is comprised of a row address and a column address. A physical address, including the row and column addresses, is accessed from the LSR. To access the DRAM paragraph at the accessed physical address, the row in the DRAM at the accessed row address location is strobed to setup and precharge the row. Following, all columns in the DRAM paragraph at the accessed physical address are strobed. After strobing the columns in a DRAM paragraph, the next physical address in the LSR, including the next row and column addresses, is accessed.

61250724, Sep 26, 2000

Jul 20, 1999

9/357690

Frank Y. Wu - Fremont CA

Seagate Technology, Inc. - Scotts Valley CA

G11C 800

36523003

A memory system and a manner of operating the memory system are provided. The memory system includes several arrays arranged in groups of columns having a column address, and rows having a row address. Operating the system involves storing blocks of data in the arrays in a way that provides contiguous logical addresses for the blocks of data. A block of data is stored in a row of a group of columns in an array. The row address is incremented and the process repeated until a row limit is reached. Next, the process is repeated with another array until blocks of data have been stored in all rows of a corresponding group of columns in the array. The column address is incremented and the row address reset, and the process repeated until a column limit is reached.

60214821, Feb 1, 2000

Jan 15, 1998

9/007618

Frank Yuhhaw Wu - Fremont CA
Steven K. Peng - Cupertino CA

Seagate Technology, Inc. - Scotts Valley CA

G06F 1200

711217

The present disclosure concerns a method and apparatus for mapping each of a plurality of logical addresses to a physical address identifying a location in a memory device. The memory device has a plurality of columns and rows, wherein each row has a plurality of data paragraphs including data and at least one parity paragraph including parity data. Each paragraph is comprised of a plurality of contiguous columns. A physical address identifies a location of a paragraph in the memory device. To map the logical addresses to physical addresses, a determination must be made as to whether the row and column portions of each logical address identify a physical address location including parity data. If a logical address identifies a physical address location in the memory device including parity data, then the logical address is incremented until the row and column portions of the logical address identify a physical address location not including parity data. The mapping is then conducted by setting the column and row portions of the physical address to the column and row portions of one of the: (i) logical address upon determining that the logical address does not identify a physical address location including parity data and (ii) the incremented logical address upon determining that the logical address identifies a physical address location including parity data.