Fei Wang

6348379, Feb 19, 2002

Feb 11, 2000

09/502153

Fei Wang - San Jose CA
Ramkumar Subramanian - San Jose CA
Yu Sun - Saratoga CA

Advanced Micro Devices, Inc. - Sunnyvale CA

H01L 21336

438257, 438263, 438264, 438265

A method for shrinking a semiconductor device is disclosed. An etch stop layer is eliminated and is replaced with a consumable second sidewall spacers so that stacked gate structures of the device can be positioned closer together, thus permitting shrinking of the device. In a preferred embodiment, the present invention provides a method for forming self-aligned contacts by forming multi-layer structures on a region on a semiconductor substrate, forming first sidewall spacers around the multi-layer structures, forming second sidewall spacers around the first sidewall spacers, forming a dielectric layer directly over the substrate and in contact with second sidewall spacers, forming an opening in the dielectric layer to expose a portion of the region on the semiconductor substrate adjacent the second sidewall spacers, and filling the opening with a conductive material to form a contact.

6348406, Feb 19, 2002

May 31, 2000

09/586264

Ramkumar Subramanian - San Jose CA
Minh Van Ngo - Fremont CA
Kashmir Sahota - Fremont CA
Yongzhong Hu - San Jose CA
Hiroyuki Kinoshita - Sunnyvale CA
Fei Wang - San Jose CA
Wenge Yang - Fremont CA

Advanced Micro Devices, Inc. - Sunnyvale CA

H01L 214763

438636, 438631, 438633, 438637

The present invention provides a method for manufacturing a semiconductor device with an anti-reflective coating (ARC) that does not need to be removed. In one embodiment, electrical devices are formed on a semiconductor substrate. A dielectric layer is then deposited over the electrical devices and the semiconductor substrate, upon which an optically transparent ARC layer of low dielectric constant is then deposited. Photoresist is then deposited on top of the ARC layer and is then photolithographically processed and subsequently developed. The dielectric layer is then etched down to the semiconductor substrate to form contacts or local interconnects. The ARC layer can subsequently be used as a hard mask and does not require removal.

6355575, Mar 12, 2002

May 22, 2000

09/575463

Fei Wang - San Jose CA
Simon S. Chan - Saratoga CA
Susan Chen - Santa Clara CA

Advanced Micro Devices, Inc. - Sunnyvale CA

H01L 21302

438712

HSQ is employed as a dielectric layer in manufacturing a high density, multi-metal layer semiconductor device. The degradation of deposited HSQ layers during formation of the semiconductor device, as from photoresist stripping using an O -containing plasma, is avoided by forming first and second dielectric layers on the HSQ layer, forming a photoresist mask on the second dielectric layer and etching to form an opening in the second dielectric layer leaving the first dielectric layer exposed. The first dielectric layer protects the HSQ from degradation during subsequent stripping.

6358362, Mar 19, 2002

Feb 29, 2000

09/515321

William G. En - Sunnyvale CA
Allison Holbrook - San Jose CA
Fei Wang - San Jose CA

Advanced Micro Devices, Inc. - Sunnyvale CA

G01I 346

156345, 20419233, 356425

An arrangement is provided for collecting, measuring and analyzing at least two specific wavelengths of optical emissions produced while etching a semiconductor wafer in a plasma chamber to determine an optimal endpoint for the etching process. The arrangement includes a sensor for gathering optical emissions, an interface for converting the intensity of optical emissions into corresponding electrical signals, and a controller for determining an optimal endpoint based on the corresponding electrical signals for the two specific wavelengths and other predetermined threshold data.

6359307, Mar 19, 2002

Jan 29, 2000

09/493436

Fei Wang - San Jose CA
Hiroyuki Kinoshita - Sunnyvale CA
Kashmir Sahota - Fremont CA
Yu Sun - Saratoga CA
Wenge Yang - Fremont CA

Advanced Micro Devices, Inc. - Sunnyvale CA

H01L 2976

257332, 438339

The present invention further provides a method for forming self-aligned contacts using a dual damascene techniques that reduces the number of process steps and results in a reduction in cycle time, cost and yield loss. In a preferred embodiment, a method for forming a contact and a channel in a dielectric layer over a region on a semiconductor substrate is provided. The contact is self-aligned. The contact and channel are formed by (1) forming a contact opening in the dielectric layer, (2) forming a channel opening in the dielectric layer, wherein the channel opening encompasses the contact opening, (3) extending the contact opening to expose a portion of the region on the semiconductor substrate; and (4) filling the contact opening and the channel opening with a conductive material to form a contact and a channel, respectively.

6362052, Mar 26, 2002

Jul 28, 2000

09/627567

Bharath Rangarajan - Santa Clara CA
Fei Wang - San Jose CA
George Kluth - Sunnyvale CA
Ursula Q. Quinto - San Jose CA

Advanced Micro Devices, Inc. - Sunnyvale CA

H01L 21336

438262, 438258, 438302, 438593

A process for fabricating a memory cell, the process includes forming an ONO layer overlying a semiconductor substrate, depositing a resist mask overlying the ONO layer, patterning the resist mask, implanting the semiconductor substrate with an n-type dopant, wherein the resist mask is used as an ion implant mask, and etching the resist mask upon implanting the semiconductor substrate with an n-type dopant. In one preferred embodiment, the etching of the resist mask includes performing a blanket anisotropic etch to reduce the thickness of the resist mask and round the edges of the resist mask. Preferably, the blanket anisotropic etch is performed using an etch including an element selected from the group consisting of nitrogen, hydrogen, chlorine, and helium.

6365505, Apr 2, 2002

Feb 21, 2001

09/780531

Fei Wang - San Jose CA
Lynne A. Okada - Sunnyvale CA
Ramkumar Subramanian - San Jose CA
Calvin T. Gabriel - Cupertino CA

Advanced Micro Devices, Inc. - Sunnyvale CA

H01L 214763

438624, 438634, 438637, 438638, 438666, 438668, 438672, 438687

A method of forming an interconnect structure in which an inorganic low k dielectric material is deposited over a conductive layer to form a first dielectric layer. An etch stop layer is formed on the first dielectric layer. The etch stop layer and the first dielectric layer are etched to form a slot via in the first dielectric layer. The slot via is longer than the width of a subsequently formed trench. An organic low k dielectric material is deposited within the slot via and over the etch stop layer to form a second dielectric layer over the slot via and the etch stop layer. The re-filled slot via is simultaneously etched with the second dielectric layer in which a trench is formed. The entire width of the trench is directly over the via. The re-opened via and the trench are filled with a conductive material.

6372631, Apr 16, 2002

Feb 7, 2001

09/778061

Fei Wang - San Jose CA
Lynne A. Okada - Sunnyvale CA
Ramkumar Subramanian - San Jose CA
Calvin T. Gabriel - Cupertino CA

Advanced Micro Devices, Inc. - Sunnyvale CA

H01L 214763

438624, 438627, 438637, 438638, 438666, 438672, 438687

An interconnect structure and method of forming the same in which a barrier diffusion layer/etch stop layer is deposited over a conductive layer. An inorganic low k dielectric material is deposited over the barrier diffusion layer/etch stop layer to form a first dielectric layer. The first dielectric layer is etched to form a via in the first dielectric layer. An organic low k dielectric material is deposited within the via and over the first dielectric layer to form a second dielectric layer over the via and the first dielectric layer. The re-filled via is simultaneously etched with the second dielectric layer in which a trench is formed. A portion of the trench is directly over the via. The re-opened via and the trench are filled with a conductive material.