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Efe S Ege

from Boise, ID
Age ~52
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Also known as:
Efe Arzum Ege, Efe Fatma Ege, Ese Ege, Efe S Simsek, Sinan Ege Efe, E Ege, Efe E, Ege Efe
Phone and address:
3320 E Heartleaf Dr, Boise, ID 83716
Related to:
Fatma Arzum Ege, 52Fatma Simsek-Ege, 53Arzum Simsekege
Connected to:
Carlton L Ege, 39Daryle J Ege, 53Elizabeth D Ege, 46Jane L Ege, 82Jeff A Ege, 52Karen A Ege, 69Kim I Ege, 65Marion L Ege, 71Robert B Ege, 70Wayne R Ege, 79

Efe Ege Phones & Addresses

  • 3320 E Heartleaf Dr, Boise, ID 83716
  • Nampa, ID
  • Meridian, ID
  • Pleasant Grove, UT
  • Corrales, NM
  • Riverton, UT
  • Herndon, VA
  • Albuquerque, NM
  • Socorro, NM
  • Carmen, ID

Work

Company: Micron technology Sep 2018 Position: Integration engineer

Education

Degree: Doctorates, Doctor of Philosophy School / High School: The University of New Mexico 2001 to 2003 Specialities: Engineering

Skills

Semiconductors • Design • Intel • Component Design • Integration

Industries

Semiconductors

Resumes

Resumes

Efe Ege Photo 1

Integration Engineer

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Location:
19750 northwest Phillips Rd, Hillsboro, OR 97124
Industry:
Semiconductors
Work:
Micron Technology
Integration Engineer
Intel Corporation Mar 2008 - Sep 2018
Micron Process Integration Engineer
Intel Corporation Jan 2004 - Sep 2006
Defect Reduction Engineer
Education:
The University of New Mexico 2001 - 2003
Doctorates, Doctor of Philosophy, Engineering
Skills:
Semiconductors
Design
Intel
Component Design
Integration

Publications

Us Patents

Low Resistance Crosspoint Architecture

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US Patent:
20210151675, May 20, 2021
Filed:
Nov 14, 2019
Appl. No.:
16/684520
Inventors:
- Boise ID, US
Patrick M. Flynn - Boise ID, US
Josiah Jebaraj Johnley Muthuraj - Meridian ID, US
Efe Sinan Ege - Boise ID, US
Kevin Lee Baker - Boise ID, US
Tao Nguyen - Boise ID, US
Davis Weymann - Boise ID, US
International Classification:
H01L 45/00
H01L 21/768
H01L 23/522
H01L 27/24
G11C 13/00
H01L 23/528
Abstract:
Methods, systems, and devices for a low resistance crosspoint architecture are described. A manufacturing system may deposit a thermal barrier material, followed by a first layer of a first conductive material, on a layered assembly including a patterned layer of electrode materials and a patterned layer of a memory material. The manufacturing system may etch a first area of the layered assembly to form a gap in the first layer of the first conductive material, the thermal barrier material, the patterned layer of the memory material, and the patterned layer of electrode materials. The manufacturing system may deposit a second conductive material to form a conductive via in the gap, where the conductive via extends to a height within the layered assembly that is above the thermal barrier material.
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Efe S Ege from Boise, ID, age ~52 Get Report