Duk Jin Kim

20210048863, Feb 18, 2021

Aug 15, 2019

16/542080

- Round Rock TX, US
Jeremiah James Bartlett - Austin TX, US
Joshua David Anderson - Round Rock TX, US
Isaac Qin Wang - Austin TX, US
Duk M. Kim - Cedar Park TX, US

G06F 1/26

An information handling system includes a controller and first, second and third devices. The devices power-on during a power-on sequence of the information handling system. During the power-on sequence, the controller provides a first power brake signal to the first device via a first power brake line, a second power brake signal to the second device via a second power brake line, and a third power brake signal to the third device via a third power brake line. The controller removes the first power brake signal from the first power brake line. In response to an expiration of a first amount of time, the controller removes the second power brake signal from the second power brake line. In response to an expiration of a second amount of time, the controller removes the third power brake signal from the third power brake line.

20200409901, Dec 31, 2020

Jun 27, 2019

16/455085

- Round Rock TX, US
Timothy M. Lambert - Austin TX, US
Duk Moon Kim - Cedar Park TX, US

G06F 13/42
G06F 9/455
G06F 15/78

In one or more embodiments, one or more systems, methods, and/or processes may determine a Peripheral Component Interconnect Express (PCIe) endpoint, associated with a PCIe destination endpoint identification, includes a field programmable gate array (FPGA); may access a partial configuration for the FPGA; may construct multiple packets that include the PCIe destination endpoint identification and respective portions of the partial configuration for the FPGA; and may provide the multiple packets to the PCIe endpoint. In one or more embodiments, the one or more systems, methods, and/or processes may further map at least a portion of the FPGA to a virtual machine. In one or more embodiments, the one or more systems, methods, and/or processes may further combine the portions of the partial configuration for the FPGA to reconstruct the partial configuration for the FPGA; and may further program the FPGA with the partial configuration for the FPGA.

20200401544, Dec 24, 2020

Jun 21, 2019

16/449134

- Round Rock TX, US
Duk M. Kim - Cedar Park TX, US

G06F 13/40
G06F 13/42

An information handling system includes first and second devices, a connectivity switch, and a baseboard management controller. The first and second devices are configured to communicate with first and second processors of the information handling system. The connectivity switch is connected between the first and second devices and the first and second processors. The connectivity switch operates in one of a plurality of configurations including a first configuration, a second configuration, and a third configuration. Each of the configurations provides a different connectivity between the first device, the second device, the first processor, and the second processor. The baseboard management controller determines a setup of the first and second devices, and provides a connectivity indication signal to the connectivity switch based on the setup of the first and second devices. The connectivity indication signal identifies one of the configurations for the connectivity switch.

20180349160, Dec 6, 2018

May 30, 2017

15/608695

- Round Rock TX, US
Gaurav CHAWLA - Austin TX, US
Duk M. KIM - Cedar Park TX, US
Srikrishna RAMASWAMY - Austin TX, US

Dell Products L.P. - Round Rock TX

G06F 9/455

In accordance with embodiments of the present disclosure, an information handling system may include a processor subsystem having access to a memory subsystem and a device communicatively coupled to the processor subsystem, the device having an endpoint assigned for access by an operating system executing on the processor subsystem such that the endpoint appears to the operating system as a logical hardware adapter, wherein the device is configured to discover a private device coupled to the device, enumerate the private device as a managed device of the device, and map a portion of a virtual address space of an operating system executing on the processor subsystem to the private device, such that the private device is abstracted to the operating system as a virtual memory address of the operating system.

20180335954, Nov 22, 2018

May 16, 2017

15/596960

- Round Rock TX, US
Shyam T. IYER - Austin TX, US
Duk M. KIM - Cedar Park TX, US

Dell Products L.P. - Round Rock TX

G06F 3/06
G06F 13/42

In accordance with embodiments of the present disclosure, a method of transmitting data in an information handling system may include receiving, at a hardware logic device from a host system processor of the information handling system, an input/output (I/O) command; storing the I/O command in a controller memory of the hardware logic device that emulates to the host system processor a controller memory of a memory storage device; communicating a notification of the I/O command to a plurality of memory storage devices communicatively coupled to the hardware logic device; coalescing a plurality of command fetch requests received from individual memory storage devices of the plurality of memory storage devices into a coalesced command fetch request; communicating the coalesced command fetch request to the controller memory; and duplicating a command fetch response from the controller memory of the coalesced command fetch request to the plurality of memory storage devices.

20180335956, Nov 22, 2018

May 17, 2017

15/597863

- Round Rock TX, US
Gaurav CHAWLA - Austin TX, US
Duk M. KIM - Cedar Park TX, US
Srikrishna RAMASWAMY - Austin TX, US

Dell Products L.P. - Round Rock TX

G06F 3/06
G06F 13/28
G06F 13/42
G06F 9/455
G06F 12/1081

A method may include, in an information handling system having an accelerator device, a physical storage media device communicatively coupled to the accelerator device, and a processor subsystem having access to the accelerator device which is coupled between the processor subsystem and the physical storage media device, responsive to an input/output command received in an address space of a storage virtual application executing as a virtual machine of a hypervisor executing on the processor subsystem from a host system executing as a second virtual machine of the hypervisor: (i) updating, by the storage virtual application, metadata associated with the input/output command including setting a host system direct memory access address corresponding to a host data buffer of the host system associated with the command; (ii) and ringing, by the storage virtual application, a doorbell for the physical storage media device.

20180336158, Nov 22, 2018

May 16, 2017

15/596984

- Round Rock TX, US
Duk M. KIM - Cedar Park TX, US
Srikrishna RAMASWAMY - Austin TX, US
Duane John VOTH - Austin TX, US

Dell Products L.P. - Round Rock TX

G06F 13/42
G06F 3/06
G06F 9/455
G06F 12/0831

An information handling system may include a processor subsystem, an attached memory, and an accelerator device communicatively coupled to the processor subsystem and interfaced between the processor subsystem and the attached memory, wherein the accelerator device is configured to: interface with a first logical software entity executing on the processor subsystem via a cache-coherent memory interface of the first logical software entity; interface with a second logical software entity executing on the processor subsystem via a non-cache-coherent memory interface of the first logical software entity; and responsive to a request to copy data to a first virtual address space of the first logical software entity from a second virtual address space of the second logical software entity, copy the data from physical address space associated with the second virtual address to the memory such that the first virtual address space maps to the data as stored on the attached memory.

20180189225, Jul 5, 2018

Jan 3, 2017

15/397003

- Round Rock TX, US
SHYAMKUMAR T. IYER - AUSTIN TX, US
DUK M. KIM - CEDAR PARK TX, US

G06F 13/42
G06F 13/40

An information handling system (IHS) and a method of transmitting data in an IHS. The method includes detecting, via a hardware logic device, a first memory transaction request from a first peripheral component interconnect express (PCIe) device to a system memory. The first memory transaction request includes a first system memory address. A second memory transaction request is detected from a second PCIe device to the system memory. The second memory transaction request includes a second system memory address. The method further includes determining if the first system memory address and the second system memory address are the same system memory address. In response to the first and second system memory addresses being the same, the first memory transaction request and the second memory transaction request are coalesced into a common memory transaction request. The common memory transaction request is issued to the system memory.