Duc The Le

50365282, Jul 30, 1991

Jan 29, 1990

7/471915

Duc N. Le - Santa Clara CA
Lordson L. Yue - Sunnyvale CA
Cirillo L. Costantino - Castro Valley CA
David P. Chengson - Mountain View CA
Aurangzeb K. Khan - Cupertino CA

Tandem Computers Incorporated - Cupertino CA

H03D 324

375119

The present invention is directed to a self-calibrating clock synchronization system that receives a periodic, digital clock signal as a reference and generates therefrom a system clock signal that dynamically tracks and is synchronized to the reference clock. The invention utilizes state machine controlled selection circuitry that comprises a plurality of predetermined delays tapped to produce a number of phase-related clock signals, and multiplexing circuitry, for selecting one of the plurality of clock signals as the system clock. A comparator compares the selected clock signal and the reference clock to determine which leads or lags the other. In response to the comparison, selection, from the plurality of clock signals, of a system clock that most clearly matches the reference signal is made.

53714172, Dec 6, 1994

Jul 2, 1993

8/087556

Russell N. Mirov - San Jose CA
Duc N. Le - Santa Clara CA
Frank Mikalauskas - San Jose CA
C. John Grebenkemper - Saratoga CA
Kinying Kwan - San Jose CA

Tandem Computers Incorporated - Cupertino CA

H03L 700

327115

A clock generator system for producing a number of multiple frequency digital clock signals for distribution to a number of synchronous, clocked devices, include two separate, substantially identically structured clock generator units that operate in lock-step unison. The digital clock signal outputs of one of the generator units are distributed to the synchronous, clocked devices and to an error detection circuit, that also receives the digital clock signals from other clock generator unit for comparison with one another. In the event an error is detected, the error detection circuit will produce an error signal to halt operation of the system with which the clock generator system is used, and reset the clock generator.

54613329, Oct 24, 1995

Oct 3, 1994

8/289823

Russell N. Mirov - San Jose CA
Duc N. Le - Santa Clara CA
Frank Mikalauskas - San Jose CA
C. John Grebenkemper - Saratoga CA
Kinying Kwan - San Jose CA

Tandem Computers Incorporated - Cupertino CA

H03L 700

327 41

A clock generator system for producing a number of multiple frequency digital clock signals for distribution to a number of synchronous, clocked devices, include two separate, substantially identically structured clock generator units that operate in lock-step unison. The digital clock signal outputs of one of the generator units are distributed to the synchronous, clocked devices and to an error detection circuit, that also receives the digital clock signals from other clock generator unit for comparison with one another. In the event an error is detected, the error detection circuit will produce an error signal to halt operation of the system with which the clock generator system is used, and reset the clock generator.

55393284, Jul 23, 1996

May 24, 1995

8/449450

Russell N. Mirov - San Jose CA
Duc N. Le - Santa Clara CA
Frank Mikalauskas - San Jose CA
C. John Grebenkemper - Saratoga CA
Kinying Kwan - San Jose CA

Tandem Computers Incorporated - Cupertino CA

H03K 1716
H03K 19003

326 30

To minimize skew and jitter imposed upon signals communicated along a printed circuit signal path a termination circuit is formed proximate the sink or receiving element of the signals. The termination circuit can be resistive, coupling the signal path to a supply power and to a ground potential.

54914426, Feb 13, 1996

May 17, 1995

8/442851

Russell N. Mirov - San Jose CA
Duc N. Le - Santa Clara CA
Frank Mikalauskas - San Jose CA
C. John Grebenkemper - Saratoga CA
Kinying Kwan - San Jose CA

Tandem Computers Incorporated - Cupertino CA

G06F 104
H03K 300

327295

A clock generator produces a plurality of clock signals from a master clock and a delayed clock version of the master clock by applying a division of the delayed version of the master clock to the data input of a flip-flop and clocking the flip-flop with the master clock. A number of plurality of clock signals are produced by applying the output of the flip-flop to the data input of an array of second flip-flops--one flip-flop of the array for each of the number of clock signals--that are clocked by the delayed version of the master clock.