David Jon Christie

6732258, May 4, 2004

Apr 2, 2001

09/824899

Kevin J. McGrath - Los Gatos CA
David S. Christie - Austin TX

Advanced Micro Devices, Inc. - Sunnyvale CA

G06F 9355

712211, 712210, 712213, 712245, 712248, 711212, 711213, 711214, 711220, 711215

A processor supports instruction pointer (IP) relative addressing in at least one operating mode of the processor. For example, in some implementations, IP relative addressing is supported in an operating mode or modes in which the address size is greater than 32 bits (e. g. up to 64 bits). In some embodiments, the displacement may be limited to less than the address size (e. g. 32 bits, in one implementation) when such operating modes are active. Code density may be higher than if the displacements were expanded, and flexibility in the placement of variables in memory may be achieved. For example, static variables may be placed in memory with flexibility, and IP relative addressing may be used to locate the static variables.

6810476, Oct 26, 2004

Apr 2, 2001

09/824862

Kevin J. McGrath - Los Gatos CA
David S. Christie - Austin TX

Advanced Micro Devices, Inc. - Sunnyvale CA

G06F 9312

712228, 712229

A processor supports at least two different state save formats. Each format stores state in the form that the state exists in one or more operating modes of the processor. The operand size of the state save and state restore instructions may be used to indicate which state format is assumed by the processor during execution of the state save and state restore instructions. In one implementation, the processor implements a processor architecture compatible with the x86 architecture with enhancements to support 64 bit addressing and processing. In modes in which 64 bit addressing is supported, segmentation is not used. In 32 bit and 16 bit modes, segmentation is used. Thus, the address of a floating point instruction and/or operand may be indicated by a segment selector or pointer or by a pointer only.

6889247, May 3, 2005

Jan 29, 2001

09/772531

David Christie - Menlo Park CA, US
Jeffrey Winner - Santa Clara CA, US

Netscape Communications Corporation - Mountain View CA

G06F015/16

709205, 709212, 709213, 709215, 709216, 370386, 370428

The present invention provides the ability to use an existing store-and-forward messaging network such as an electronic mail system to replicate data between computer sites. The replication provided by the present invention can be used with software applications, such as workgroup applications, to replicate data located on multiple sites. Workgroup replication data is sent to other sites via electronic mail (“e-mail”) messages. The present invention provides reliability features to handle errors in electronic mail transmissions. For example, the present invention provides the ability to reassemble objects at a replication site such that an object and all of its dependencies exist prior to the object's use at the site. Messages referred to as “ACK” messages are used to communicate a site's state and to provide other control information. Each site maintains latency information to determine transmission failures.

7100028, Aug 29, 2006

Apr 2, 2001

09/824978

Kevin J. McGrath - Los Gatos CA, US
David S. Christie - Austin TX, US

Advanced Micro Devices, Inc. - Sunnyvale CA

G06F 9/38
G06F 9/00

712229, 712245

A processor executes a system call instruction. The processor includes at least two registers in which target addresses may be stored, and selects the target address from one of the registers responsive to the operating mode. Different target addresses may be programmed into the registers, and thus the operating mode of the code sequence may be indicated by which target address is selected.

7298922, Nov 20, 2007

Jul 7, 2004

10/886999

John Elmer Lindgren - San Jose CA, US
David Nicholas Christie - Brentwood CA, US

Lockheed Martin Corporation - Bethesda MD

G06K 9/32

382294, 382164, 382284, 382291, 358518, 358520, 342 25 A, 342409

Method and system for generating synthetic panchromatic imagery. A method for making a multi-spectral image includes capturing a panchromatic image of an imaging target. Additionally, the method includes capturing at least a first spectral image of the imaging target in a first spectral bandwidth, and capturing at least a second spectral image of the imaging target in a second spectral bandwidth. Also, the method includes determining at least a first spectral weight and a second spectral weight for the first spectral image and the second spectral image respectively. Additionally, the method includes generating a synthetic panchromatic image, determining a registration offset between the synthetic panchromatic image and the captured panchromatic image, warping the first spectral image and the second spectral image, and generating a multi-spectral image.

7496966, Feb 24, 2009

Apr 18, 2003

10/419120

Kevin J. McGrath - Los Gatos CA, US
David S. Christie - Austin TX, US
Geoffrey S. Strongin - Austin TX, US

Advanced Micro Devices, Inc. - Sunnyvale CA

G06F 7/04
G06F 12/00

726 27, 711100, 711145

A method for controlling operation of a secure execution mode-capable processor includes receiving access requests to a plurality of addressable locations within a system memory. The method may further include preventing the access requests from completing in response to determining that the secure execution mode-capable processor is operating in a secure execution mode.

7603550, Oct 13, 2009

Apr 18, 2003

10/419082

Kevin J. McGrath - Los Gatos CA, US
Geoffrey S. Strongin - Austin TX, US
Dale E. Gulick - Austin TX, US
William A. Hughes - Burlingame CA, US
David S. Christie - Austin TX, US

Advanced Micro Devices, Inc. - Sunnyvale CA

H04L 9/00
H04L 9/32

713164, 713190

A computer system includes a processor which may initialize a secure execution mode by executing a security initialization instruction. Further, the processor may operate in the secure execution mode by executing a secure operating system code segment. The computer system also includes an input/output (I/O) interface coupled to the processor via an I/O link. The I/O interface may receive transactions performed as a result of the execution of the security initialization instruction. The transactions include at least a portion of the secure operating system code segment. The I/O interface may also determine whether the processor is a source of the transactions. The computer system further includes a security services processor coupled to the I/O interface via a peripheral bus. The I/O interface may convey the transactions to the security services processor dependent upon determining that the processor is the source of the transactions.

7603551, Oct 13, 2009

Apr 18, 2003

10/419121

Kevin J. McGrath - Los Gatos CA, US
Geoffrey S. Strongin - Austin TX, US
David S. Christie - Austin TX, US
William A. Hughes - San Jose CA, US
Dale E. Gulick - Austin TX, US

Advanced Micro Devices, Inc. - Sunnyvale CA

G06F 9/44
H04L 29/06

713164

The initialization of a computer system including a secure execution mode-capable processor includes storing a secure operating system code segment loader to a plurality of locations corresponding to a particular range of addresses within a system memory. The method also includes executing a security initialization instruction. Executing the security initialization instruction may cause several operations to be performed including transmitting a start transaction including a base address of the particular range of addresses. In addition, executing the security instruction may also cause another operation to be performed including retrieving the secure operating system code segment loader from the system memory and transmitting the secure operating system code segment loader for validation as a plurality of data transactions.