Dat Tan Tran

7009889, Mar 7, 2006

May 28, 2004

10/857245

Dat Tran - San Jose CA, US
Kiran Ponnuru - Sunnyvale CA, US
Jian Chen - San Jose CA, US
Jeffrey W. Lutze - San Jose CA, US
Jun Wan - Sunnyvale CA, US

Sandisk Corporation - Sunnyvale CA

G11C 16/04

36518529, 36518517, 36518521

Systems and methods in accordance with various embodiments can provide for comprehensive erase verification and defect detection in non-volatile semiconductor memory. In one embodiment, the results of erasing a group of storage elements is verified using a plurality of test conditions to better detect defective and/or insufficiently erased storage elements of the group. For example, the results of erasing a NAND string can be verified by testing charging of the string in a plurality of directions with the storage elements biased to turn on if in an erased state. If a string of storage elements passes a first test process or operation but fails a second test process or operation, the string can be determined to have failed the erase process and possibly be defective. By testing charging or conduction of the string in a plurality of directions, defects in any transistors of the string that are masked under one set of conditions may be exposed under a second set of bias conditions. For example, a string may pass an erase verification operation but then be read as including one or more programmed storage elements.

7450435, Nov 11, 2008

Dec 21, 2005

11/316162

Dat Tran - San Jose CA, US
Kiran Ponnuru - Sunnyvale CA, US
Jian Chen - San Jose CA, US
Jeffrey W. Lutze - San Jose CA, US
Jun Wan - Sunnyvale CA, US

SanDisk Corporation - Milpitas CA

G11C 11/34

36518529, 36518517, 36518533

Systems and methods in accordance with various embodiments can provide for comprehensive erase verification and defect detection in non-volatile semiconductor memory. In one embodiment, the results of erasing a group of storage elements is verified using a plurality of test conditions to better detect defective and/or insufficiently erased storage elements of the group. For example, the results of erasing a NAND string can be verified by testing charging of the string in a plurality of directions with the storage elements biased to turn on if in an erased state. If a string of storage elements passes a first test process or operation but fails a second test process or operation, the string can be determined to have failed the erase process and possibly be defective. By testing charging or conduction of the string in a plurality of directions, defects in any transistors of the string that are masked under one set of conditions may be exposed under a second set of bias conditions. For example, a string may pass an erase verification operation but then be read as including one or more programmed storage elements.

7463532, Dec 9, 2008

Dec 21, 2005

11/316119

Dat Tran - San Jose CA, US
Kiran Ponnuru - Sunnyvale CA, US
Jian Chen - San Jose CA, US
Jeffrey W. Lutze - San Jose CA, US
Jun Wan - Sunnyvale CA, US

SanDisk Corporation - Milpitas CA

G11C 11/34

36518529, 36518517, 36518533

Systems and methods in accordance with various embodiments can provide for comprehensive erase verification and defect detection in non-volatile semiconductor memory. In one embodiment, the results of erasing a group of storage elements is verified using a plurality of test conditions to better detect defective and/or insufficiently erased storage elements of the group. For example, the results of erasing a NAND string can be verified by testing charging of the string in a plurality of directions with the storage elements biased to turn on if in an erased state. If a string of storage elements passes a first test process or operation but fails a second test process or operation, the string can be determined to have failed the erase process and possibly be defective. By testing charging or conduction of the string in a plurality of directions, defects in any transistors of the string that are masked under one set of conditions may be exposed under a second set of bias conditions. For example, a string may pass an erase verification operation but then be read as including one or more programmed storage elements.

7508720, Mar 24, 2009

Dec 21, 2005

11/316475

Dat Tran - San Jose CA, US
Kiran Ponnuru - Sunnyvale CA, US
Jian Chen - San Jose CA, US
Jeffrey W. Lutze - San Jose CA, US
Jun Wan - Sunnyvale CA, US

SanDisk Corporation - Milpitas CA

G11C 11/34

36518529, 36518517, 36518521

Systems and methods in accordance with various embodiments can provide for comprehensive erase verification and defect detection in non-volatile semiconductor memory. In one embodiment, the results of erasing a group of storage elements is verified using a plurality of test conditions to better detect defective and/or insufficiently erased storage elements of the group. For example, the results of erasing a NAND string can be verified by testing charging of the string in a plurality of directions with the storage elements biased to turn on if in an erased state. If a string of storage elements passes a first test process or operation but fails a second test process or operation, the string can be determined to have failed the erase process and possibly be defective. By testing charging or conduction of the string in a plurality of directions, defects in any transistors of the string that are masked under one set of conditions may be exposed under a second set of bias conditions. For example, a string may pass an erase verification operation but then be read as including one or more programmed storage elements.

7512014, Mar 31, 2009

Dec 21, 2005

11/316069

Dat Tran - San Jose CA, US
Kiran Ponnuru - Sunnyvale CA, US
Jian Chen - San Jose CA, US
Jeffrey W. Lutze - San Jose CA, US
Jun Wan - Sunnyvale CA, US

SanDisk Corporation - Milpitas CA

G11C 11/34

36518529, 36518533, 36518904

Systems and methods in accordance with various embodiments can provide for comprehensive erase verification and defect detection in non-volatile semiconductor memory. In one embodiment, the results of erasing a group of storage elements is verified using a plurality of test conditions to better detect defective and/or insufficiently erased storage elements of the group. For example, the results of erasing a NAND string can be verified by testing charging of the string in a plurality of directions with the storage elements biased to turn on if in an erased state. If a string of storage elements passes a first test process or operation but fails a second test process or operation, the string can be determined to have failed the erase process and possibly be defective. By testing charging or conduction of the string in a plurality of directions, defects in any transistors of the string that are masked under one set of conditions may be exposed under a second set of bias conditions. For example, a string may pass an erase verification operation but then be read as including one or more programmed storage elements.

20220309666, Sep 29, 2022

Jun 15, 2022

17/841610

- South San Francisco CA, US
Mandy Man Chu YIM - San Mateo CA, US
Bibi EPHRAIM - Oakland CA, US
Dat TRAN - San Mateo CA, US
Xinyu LIU - Pleasanton CA, US
David SHAW - San Francisco CA, US

G06T 7/00
G06T 7/11
G06T 7/73
G06V 10/25
G06V 10/20
G06V 10/26
G06V 10/46

A method includes, by a computing system, receiving a querying image depicting a sampling area, processing the querying image using a single cluster detection model to identify one or more regions of the querying image depicting a cluster in the sampling area, processing the one or more regions using a cluster verification deep-learning model to determine whether each depicted cluster is a cell cluster, and determining that exactly one of the identified one or more regions depicts a cluster that is a cell cluster. The method further includes processing the region depicting the cell cluster using a morphology deep-learning model to determine that there is only one cell in the cell cluster and to determine that die morphology of the cell is acceptable.