Daniel Sai Fung

7317394, Jan 8, 2008

Jan 4, 2005

11/029867

Liang Seng Koh - Fremont CA, US
Fu-Liang Cho - San Jose CA, US
Daniel Fung - Redwood City CA, US
Hsin Pan - Fremont CA, US

RFCyber Corp. - Fremont CA

G08B 13/14

3405721, 717120

A system, method and related software architecture are disclosed as a platform for developing and deploying RFID-enabled software applications. The platform is a framework between these applications and their connected physical RFID devices. The runtime version of this platform can be thought of as a logical RFID device. The platform allows RFID-enabled applications securely communicate with physical RFID devices to monitor their status and to access their tag data. The platform includes externalized APIs for accessing tag data, an event manager to alert applications of events coming from RFID devices and tags, data manager to filter and reconcile data returned from physical RFID readers before relaying them to applications, device manager to monitor the RFID device status for network management, and secured communication channels with data encryption. The deployed RFID-enabled applications can recognize user identification via the RFID tags then access data of selected RFID tags within a secured infrastructure.

7443759, Oct 28, 2008

Apr 26, 2007

11/740892

Joseph B. Rowlands - Santa Clara CA, US
Laurent R. Moll - San Jose CA, US
John Gregory Favor - Scotts Valley CA, US
Daniel Fung - Fremont CA, US

Sun Microsystems, Inc. - Santa Clara CA

G11C 5/14
G11C 8/00

365227, 365226, 36523003

A reduced-power memory (such as for a cache memory system of a processor or a microprocessor) provides per-sector ground control to advantageously reduce power consumption. Selective power control of a plurality of sectors comprised in the reduced-power memory is responsive to a subset of address bits for accessing the memory. The selective power control individually powers-up a selected one of the sectors in response to an access, and then powers-down the selected sector when the access is complete. The power-up is via a decrease in ground potential from a retention level to an access level. Time needed to vary the ground potential is optionally masked by providing address information used by the selective power control in advance of providing other address information. For example, in a cache, a tag access is overlapped with power-up of a selected sector, thus masking latency of powering up the selected sector.

7663961, Feb 16, 2010

Apr 26, 2007

11/740901

Joseph B. Rowlands - Santa Clara CA, US
Laurent R. Moll - San Jose CA, US
John Gregory Favor - Scotts Valley CA, US
Daniel Fung - Fremont CA, US

Sun Microsystems, Inc. - Santa Clara CA

G11C 5/14
G11C 8/00

365227, 365226, 36523003

A reduced-power memory (such as for a cache memory system of a processor or a microprocessor) provides per-sector power/ground control and early address to advantageously reduce power consumption. Selective power control of sectors comprised in the reduced-power memory is responsive to a subset of address bits used to access the memory. The selective power control individually powers-up a selected one of the sectors in response to an access, and then powers-down the selected sector when the access is complete. The power-up is via an increase of differential between power and ground levels from a retention differential to an access differential. Time needed to vary the differential is masked by providing address information used by the selective power control in advance of providing other address information. For example, in a cache, a tag access is overlapped with power-up of a selected sector, thus masking latency of powering up the selected sector.

7672187, Mar 2, 2010

Oct 31, 2007

11/932967

Yolin Lih - San Jose CA, US
Ajay Bhatia - Santa Clara CA, US
Dennis Wendell - Sunnyvale CA, US
Jun Liu - Santa Clara CA, US
Daniel Fung - Santa Clara CA, US
Shyam Balasubramanian - Santa Clara CA, US

Sun Microsystems, Inc. - Santa Clara CA

G11C 5/14

365226, 365154, 365156

An elastic power header device and methods of operation are provided to improve both the read and the write margin of static random access memory (SRAM) cells by increasing read stability, reducing read disturbance and improving the Signal to Noise Margin (SNM) figure of merit. For example, various implementations of an elastic power header device are utilized as programmable resistances to permit the power supply lines to reach a maximum voltage. Allowing the power supply lines to reach the reference voltage allows more flexibility in read margin, write margin and read stability. Furthermore, this additional flexibility can be controlled by means for adjusting a voltage. This adjustment voltage can fine-tune the programmable resistances so that the read margin and the write margin can be more conveniently controlled.

7869263, Jan 11, 2011

Nov 9, 2007

11/938196

Yolin Lih - San Jose CA, US
Ajay Bhatia - Santa Clara CA, US
Dennis Wendell - Sunnyvale CA, US
Jun Liu - Santa Clara CA, US
Daniel Fung - Santa Clara CA, US
Shyam Balasubramanian - Santa Clara CA, US

Oracle America, Inc. - Redwood City CA

G11C 11/00

365154, 365156, 365226

An elastic power header device and methods of operation are provided to improve the read margin of static random access memory (SRAM) cells by increasing read stability, reducing read disturbance and improving the Signal to Noise Margin (SNM) figure of merit. For example, various implementations of an elastic power header device are utilized as programmable resistances to permit the power supply lines to reach a maximum voltage. Allowing the power supply lines to reach the reference voltage allows more flexibility in read margin and read stability. Furthermore, this additional flexibility can be controlled by means for adjusting a voltage. This adjustment voltage can fine-tune the programmable resistances so that the read margin can be more conveniently controlled.

7952910, May 31, 2011

Oct 31, 2007

11/932555

Yolin Lih - San Jose CA, US
Dennis Wendell - Sunnyvale CA, US
Jun Liu - Cupertino CA, US
Daniel Fung - Fremont CA, US
Ajay Bhatia - Santa Clara CA, US
Shyam Balasubramanian - Santa Clara CA, US

Oracle America, Inc. - Redwood City CA

G11C 11/00

365154, 365226, 365227

A memory device having a split power switch is provided to improve the writeability of static random access memory (SRAM) cells without adversely compromising their stability. For example, various split power switch circuits are used to permit the voltage or current of a power supply line connected with one side of an SRAM cell to drop during write operations. This drop weakens one side of the SRAM cell and reduces the drive-fight between transistors of the SRAM cell and external write circuitry. As a result, the minimum voltage for writing new logic states into the SRAM cell is reduced to permit overall lower operating voltages for the SRAM cell and related circuitry. By continuing to maintain a second side of the SRAM cell at the reference voltage or current, the SRAM cell can successfully switch to a newly written logic state.

20080266995, Oct 30, 2008

Oct 31, 2007

11/932643

Yolin Lih - San Jose CA, US
Dennis Wendell - Sunnyvale CA, US
Jun Liu - Cupertino CA, US
Daniel Fung - Fremont CA, US
Ajay Bhatia - Santa Clara CA, US
Shyam Balasubramanian - Santa Clara CA, US

G11C 5/14

365226

An approach to selectively powering a memory device is provided to improve the writeability of static random access memory (SRAM) cells without adversely compromising their stability. For example, various methods are provided to permit the voltage or current of a power supply line connected with one side of an SRAM cell to drop during write operations. This drop weakens one side of the SRAM cell and reduces the drive-fight between transistors of the SRAM cell and external write circuitry. As a result, the minimum voltage for writing new logic states into the SRAM cell is reduced to permit overall lower operating voltages for the SRAM cell and related circuitry. By continuing to maintain a second side of the SRAM cell at the reference voltage or current, the SRAM cell can successfully switch to a newly written logic state.

20130235680, Sep 12, 2013

Mar 9, 2012

13/416270

Hoyeol CHO - Palo Alto CA, US
Ioannis Orginos - Sunnyvale CA, US
Daniel Fung - Fremont CA, US

ORACLE INTERNATIONAL CORPORATION - REDWOOD SHORES CA

G11C 7/00

365191, 365194

Systems and methods are described herein that reduce the read latency of a cache by separating read and write column select signals that cause the cache to initiate certain read and write operations, respectively.