Dan Tuan Tran

56665156, Sep 9, 1997

Dec 4, 1996

8/759996

Theodore Curt White - Tustin CA
Jayesh Vrajlal Sheth - Mission Viejo CA
Kha Nguyen - Anaheim CA
Dan Trong Tran - Laguna Niguel CA

Unisys Corporation - Blue Bell PA

G06F 1214
G06F 1318

711152

Apparatus and method are provided for preventing access to a memory location while that memory location is being modified, updated, etc. When a peripheral device wishes to accomplish such a change at a memory location, it provides the changed data and its intended memory address to an input/output unit. The input/output unit includes a plurality of separately controlled multiplexers, the number of multiplexers being preferably selected to correspond to the size (in bits) of a memory data word or packet divided by the size (in bits) of a peripheral data word. The input/output unit reads the data at the requested memory location into an input buffer, combines the portions of that data not to be modified with the data provided by the peripheral, and sends the result back to the same memory location. During this Read-Modify-Write operation, the input/output unit also monitors the system bus for any attempts or requests to read data from, or write data to, the memory address for which the Read-Modify-Write operation is being performed. In such event, a signal is sent to the module making such attempt or request, asking or telling that module to wait.

55984215, Jan 28, 1997

Feb 17, 1995

8/390712

Dan T. Tran - Laguna Niguel CA
Wayne C. Datwyler - Laguna Niguel CA
Long V. Ha - Walnut CA

Unisys Corporation - Blue Bell PA

G01R 3128

371 223

The logic circuitry of an IC chip is connected to JTAG register chains which hold state information on each portion of the logic circuitry therein. A JTAG Tracker Module is connected to the controls of each of the JTAG register chains enabling a programmer-operator to read the present state of each JTAG register chain and enabling a readout of the logic circuits condition in a single clock period.

54955734, Feb 27, 1996

Aug 5, 1994

8/286855

Wayne C. Datwyler - Laguna Niguel CA
Long V. Ha - Walnut CA
Dan T. Tran - Laguna Niguel CA

Unisys Corporation - Blue Bell PA

G11C 2900

39518501

An error logging system where errors are captured on dual system busses operating at a lower clock rate (16 MHz) than the processor which receives the error information. The system functions to substantially reduce the loads on the processor in addition to maximizing the use of the system bus drivers which are pin-constrained. The processor operates at a higher clock rate (32 MHz). Processor commands to read error data from an error log register are synchronized down to the 16 MHz rate, then enabled onto a processor bus after a second synchronization operation back to the higher (32 MHz) rate. Provision is made for identifying several different types of error categories. An expandable error log register system is provided which uses selected bit positions to identify types of errors logged to the processor which also enables expansitivity for adding in future types of errors into the error logging system and renders compatibility for a processor operating at first clock rate with error data sensed at a second clock rate.

52936210, Mar 8, 1994

Jan 11, 1993

8/002566

Theodore C. White - Tustin CA
Jayesh V. Sheth - Mission Viejo CA
Paul B. Ricci - Laguna Niguel CA
Dan T. Tran - Laguna Niguel CA

Unisys Corporation - Blue Bell PA

G06F 1342

395650

A User bus lockout prevention mechanism for use in a time-shared bus, multiple bus User, computer architecture where bus Users have private cache systems which perform a cache cycle when a WRITE TO MEMORY instruction occurs on the bus to determine if data cached from main memory has been overwritten in main memory. A User can be locked out from use of the bus if a synchronism occurs between repetitive cache cycles and periodicity of the request Retry mechanism of the User. Bus lockout is prevented by controlling the Retry mechanism of the User to retry requests in accordance with a sequence of varying retry wait intervals. The sequence comprises bursts of short wait intervals interleaved with long wait intervals, the sequence beginning with a burst of short wait intervals. The wait interval durations of the first and second occurring bursts are interleaved with respect to each other. The second occurring long wait is longer than the first occurring long wait.

55112242, Apr 23, 1996

Mar 16, 1995

8/406811

Dan T. Tran - Laguna Niguel CA
Paul B. Ricci - Laguna Niguel CA
Jayesh V. Sheth - Mission Viejo CA
Theodore C. White - Tustin CA
Richard A. Cowgill - Lake Forest CA

Unisys Corporation - Blue Bell PA

G06F 1116

395800

A network of digital modules having store-through and non-store-through cache memories, is provided with intercommunication capability by means of two sets of system busses each of which are replicates of each other. The system busses provide a higher throughput by both being available to each of the digital modules so that a requesting digital module can alternately use a second system bus if the first system bus happens to be busy. Failure of one system bus will allocate transmission service to the second operating system bus thus providing redundancy. Alternatively, each of the system busses can be isolated for partitioning the digital modules into two different operating systems which are independent of each other.

58095330, Sep 15, 1998

Feb 11, 1997

8/797216

Dan Trong Tran - Laguna Niguel CA
Paul Bernard Ricci - Laguna Niguel CA
Jayesh Vrajlal Sheth - Mission Viejo CA
Theodore Curt White - Tustin CA
Richard Allen Cowgill - Lake Forest CA

Unisys Corporation - Blue Bell PA

G06F 1316

711141

A multi-module network having dual system busses using a common bus protocol which supports processor modules using a store-through cache memory and processor modules using a non-store-through cache memory which includes interface modules including a spy unit for maintaining cache coherency and arbiter modules so that any particular module is not starved out. A maintenance processor organizes the network as a joined system where both the store-through and non-store through processor units can utilize either one of the dual system busses or a split system where one bus is dedicated to the store-through processor units and one bus is dedicated to the non-store through processor units.

54447224, Aug 22, 1995

Feb 17, 1993

8/018949

Dan T. Tran - Laguna Niguel CA

Unisys Corporation - Blue Bell PA

H04Q 1104

39518318

A memory module is used in multiples on a bus in a data processing system. Each memory module comprises a plurality of storage cells, an input circuit for receiving a read command and a read address from the bus, and a compare circuit which generates a match signal when the read address is within a selectable address range for the storage cells. Also, the module further includes: a control circuit, coupled to the compare circuit, which responds to the match signal by almost always executing the read command in a small time interval on the bus and occasionally executing the read command in a long time interval. Further, the module includes a bus transmit circuit, coupled to the control circuit, for sending a control signal on the bus if the control circuit selects the long time interval. Also, the module includes an error circuit, coupled to the control circuit and the bus, for setting an error flag if the control circuit selects the short time interval and, during that short time interval, the control signal is detected on the bus from another module in the memory system.

55532497, Sep 3, 1996

Mar 8, 1995

8/400700

Wayne C. Datwyler - Laguna Niguel CA
Dan T. Tran - Laguna Niguel CA
Long V. Ha - Walnut CA

Unisys Corporation - Blue Bell PA

G06F 1342

395308

A single chip data path gate array interface links a central processing unit, operating at a first clock rate and single word protocol, to dual system busses operating at a second clock rate and multiple-word protocol. The data path interface holds command, data and message registers, controlled by external logic, in an input channel pathway and an output channel pathway. The interface chip is basically limited to registers and multiplexers making it flexible for use in different architectures such as both Store-Through and Non-Store-Through cache protocols. In addition, such a simplified chip is simple to fabricate and to maintain free of defects.