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Dan Luu

from San Jose, CA
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Related to:
Loc V Nguyen, 77Huong T Nguyen, 44Michael V Nguyen, 61David V Nguyen, 88Hung V Nguyen, 54Nam H Luu, 63Jian E Wu, 43Christine Luu, 50
Connected to:
Alain N Luu, 52Alex H Luu, 50Alice S Luu, 60Annie H Luu, 52Calvan N Luu, 49Ching S Luu, 67Chuyen Luu, 52Claire Luu, 46Courtney N Luu, 57Cynthia L Luu, 56

Dan Luu Phones & Addresses

  • San Jose, CA

Professional Records

Medicine Doctors

Dan Luu Photo 1

Dan N. Luu

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Specialties:
Family Medicine
Work:
Graybill Medical GroupGraybill Medical Group Tri-City Office
2067 W Vis Way STE 250, Vista, CA 92083
(866) 228-2236 (phone), (760) 330-9330 (fax)
Education:
Medical School
Temple University School of Medicine
Graduated: 2008
Procedures:
Destruction of Benign/Premalignant Skin Lesions
Destruction of Lesions on the Anus
Electrocardiogram (EKG or ECG)
Hearing Evaluation
Skin Tags Removal
Vaccine Administration
Conditions:
Abnormal Vaginal Bleeding
Acute Pharyngitis
Acute Sinusitis
Acute Upper Respiratory Tract Infections
Allergic Rhinitis
Languages:
English
Spanish
Tagalog
Vietnamese
Description:
Dr. Luu graduated from the Temple University School of Medicine in 2008. She works in Vista, CA and specializes in Family Medicine. Dr. Luu is affiliated with Palomar Health Downtown Hospital Campus.

Resumes

Resumes

Dan Luu Photo 2

System Design Engineer

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Location:
1537 Four Oaks Rd, San Jose, CA 95131
Industry:
E-Learning
Work:
Intel Corporation Mar 2012 - Aug 2013
Hardware Engineer at Intel Corporation
Nvidia Mar 2012 - Aug 2013
System Design Engineer
Unknow Aug 2009 - Sep 2011
Product Engineer For Image Sensor
Education:
Northwestern Polytechnic University
Languages:
English
Dan Luu Photo 3

Dan Luu

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Dan Luu Photo 4

Dilettante At Hacker School

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Position:
Dilettante at Hacker School
Location:
New York, New York
Industry:
Research
Work:
Hacker School - Greater New York City Area since Mar 2013
Dilettante
Centaur Technology Nov 2005 - Feb 2013
Member of Technical Staff
University of Texas at Austin Jul 2009 - Aug 2010
Research Assistant
Ultrafast Optics and Optical Fiber Communications Laboratory Sep 2003 - May 2005
Research Assistant
IBM May 2003 - Aug 2003
Intern, Server Group
Education:
Purdue University 2003 - 2005
MS, Electrical and Computer Engineering (Optics) University of Wisconsin-Madison 2000 - 2003
BS, Mathematics, Computer Engineering
Skills:
Algorithms
Scala
x86 Assembly
Microcode
RTL design
Computer Architecture
Common Sense
Machine Learning
Debugging
Ruby
Verilog
Dance
Statistics
CMOS
Julia
Rust
PHP
Notepad
Concurrent Programming
Learning Theory
Writing
FPGA
R
Security
Combinatorics
Optics
Neural Networks
Honor & Awards:
MCD Fellowship Burton D. Morgan Entrepreneurship Competition Semi-Finalist David Ross Fellowship (5 years of funding) Dean's list each full-time semester AP Scholar with distinction

Publications

Us Patents

Neural Network Processor

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US Patent:
20220366255, Nov 17, 2022
Filed:
Jul 27, 2022
Appl. No.:
17/874573
Inventors:
- Mountain View CA, US
Norman Paul Jouppi - Palo Alto CA, US
Andrew Everett Phelps - Middleton WI, US
Reginald Clifford Young - Palo Alto CA, US
Thomas Norrie - San Jose CA, US
Gregory Michael Thorson - Waunakee WI, US
Dan Luu - Madison WI, US
International Classification:
G06N 3/08
G06F 15/80
G06N 3/063
G06N 5/04
Abstract:
A circuit for performing neural network computations for a neural network comprising a plurality of neural network layers, the circuit comprising: a matrix computation unit configured to, for each of the plurality of neural network layers: receive a plurality of weight inputs and a plurality of activation inputs for the neural network layer, and generate a plurality of accumulated values based on the plurality of weight inputs and the plurality of activation inputs; and a vector computation unit communicatively coupled to the matrix computation unit and configured to, for each of the plurality of neural network layers: apply an activation function to each accumulated value generated by the matrix computation unit to generate a plurality of activated values for the neural network layer.

Neural Network Processor

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US Patent:
20210019618, Jan 21, 2021
Filed:
Jun 29, 2020
Appl. No.:
16/915161
Inventors:
- Mountain View CA, US
Norman Paul Jouppi - Palo Alto CA, US
Andrew Everett Phelps - Middleton WI, US
Reginald Clifford Young - Palo Alto CA, US
Thomas Norrie - Mountain View CA, US
Gregory Michael Thorson - Waunakee WI, US
Dan Luu - Madison WI, US
International Classification:
G06N 3/08
G06F 15/80
G06N 3/063
G06N 5/04
Abstract:
A circuit for performing neural network computations for a neural network comprising a plurality of neural network layers, the circuit comprising: a matrix computation unit configured to, for each of the plurality of neural network layers: receive a plurality of weight inputs and a plurality of activation inputs for the neural network layer, and generate a plurality of accumulated values based on the plurality of weight inputs and the plurality of activation inputs; and a vector computation unit communicatively coupled to the matrix computation unit and configured to, for each of the plurality of neural network layers: apply an activation function to each accumulated value generated by the matrix computation unit to generate a plurality of activated values for the neural network layer.

Neural Network Processor

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US Patent:
20200218981, Jul 9, 2020
Filed:
Mar 19, 2020
Appl. No.:
16/824411
Inventors:
- Mountain View CA, US
Norman Paul Jouppi - Palo Alto CA, US
Andrew Everett Phelps - Middleton WI, US
Reginald Clifford Young - Palo Alto CA, US
Thomas Norrie - Mountain View CA, US
Gregory Michael Thorson - Waunakee WI, US
Dan Luu - Madison WI, US
International Classification:
G06N 3/08
G06N 5/04
G06N 3/063
G06F 15/80
Abstract:
A circuit for performing neural network computations for a neural network comprising a plurality of neural network layers, the circuit comprising: a matrix computation unit configured to, for each of the plurality of neural network layers: receive a plurality of weight inputs and a plurality of activation inputs for the neural network layer, and generate a plurality of accumulated values based on the plurality of weight inputs and the plurality of activation inputs; and a vector computation unit communicatively coupled to the matrix computation unit and configured to, for each of the plurality of neural network layers: apply an activation function to each accumulated value generated by the matrix computation unit to generate a plurality of activated values for the neural network layer.

Neural Network Processor

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US Patent:
20200057942, Feb 20, 2020
Filed:
Oct 25, 2019
Appl. No.:
16/663876
Inventors:
- Mountain View CA, US
Norman Paul Jouppi - Palo Alto CA, US
Andrew Everett Phelps - Middleton WI, US
Reginald Clifford Young - Palo Alto CA, US
Thomas Norrie - Mountain View CA, US
Gregory Michael Thorson - Waunakee WI, US
Dan Luu - Madison WI, US
International Classification:
G06N 3/08
G06N 5/04
G06N 3/063
G06F 15/80
Abstract:
A circuit for performing neural network computations for a neural network comprising a plurality of neural network layers, the circuit comprising: a matrix computation unit configured to, for each of the plurality of neural network layers: receive a plurality of weight inputs and a plurality of activation inputs for the neural network layer, and generate a plurality of accumulated values based on the plurality of weight inputs and the plurality of activation inputs; and a vector computation unit communicatively coupled to the matrix computation unit and configured to, for each of the plurality of neural network layers: apply an activation function to each accumulated value generated by the matrix computation unit to generate a plurality of activated values for the neural network layer.

Neural Network Processor

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US Patent:
20190354862, Nov 21, 2019
Filed:
Aug 1, 2019
Appl. No.:
16/529782
Inventors:
- Mountain View CA, US
Norman Paul Jouppi - Palo Alto CA, US
Andrew Everett Phelps - Middleton WI, US
Reginald Clifford Young - Palo Alto CA, US
Thomas Norrie - Mountain View CA, US
Gregory Michael Thorson - Waunakee WI, US
Dan Luu - Madison WI, US
International Classification:
G06N 3/08
G06N 5/04
G06F 15/80
G06N 3/063
Abstract:
A circuit for performing neural network computations for a neural network comprising a plurality of neural network layers, the circuit comprising: a matrix computation unit configured to, for each of the plurality of neural network layers: receive a plurality of weight inputs and a plurality of activation inputs for the neural network layer, and generate a plurality of accumulated values based on the plurality of weight inputs and the plurality of activation inputs; and a vector computation unit communicatively coupled to the matrix computation unit and configured to, for each of the plurality of neural network layers: apply an activation function to each accumulated value generated by the matrix computation unit to generate a plurality of activated values for the neural network layer.

Neural Network Processor

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US Patent:
20180046907, Feb 15, 2018
Filed:
Aug 25, 2017
Appl. No.:
15/686615
Inventors:
- Mountain View CA, US
Norman Paul Jouppi - Palo Alto CA, US
Andrew Everett Phelps - Middleton WI, US
Reginald Clifford Young - Palo Alto CA, US
Thomas Norrie - Mountain View CA, US
Gregory Michael Thorson - Waunakee WI, US
Dan Luu - Madison WI, US
International Classification:
G06N 3/063
G06F 15/80
Abstract:
A circuit for performing neural network computations for a neural network comprising a plurality of neural network layers, the circuit comprising: a matrix computation unit configured to, for each of the plurality of neural network layers: receive a plurality of weight inputs and a plurality of activation inputs for the neural network layer, and generate a plurality of accumulated values based on the plurality of weight inputs and the plurality of activation inputs; and a vector computation unit communicatively coupled to the matrix computation unit and configured to, for each of the plurality of neural network layers: apply an activation function to each accumulated value generated by the matrix computation unit to generate a plurality of activated values for the neural network layer.

Neural Network Processor

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US Patent:
20170103313, Apr 13, 2017
Filed:
Dec 22, 2016
Appl. No.:
15/389202
Inventors:
- Mountain View CA, US
Norman Paul Jouppi - Palo Alto CA, US
Andrew Everett Phelps - Middleton WI, US
Reginald Clifford Young - Palo Alto CA, US
Thomas Norrie - Mountain View CA, US
Gregory Michael Thorson - Waunakee WI, US
Dan Luu - Madison WI, US
International Classification:
G06N 3/08
G06N 5/04
Abstract:
A circuit for performing neural network computations for a neural network comprising a plurality of neural network layers, the circuit comprising: a matrix computation unit configured to, for each of the plurality of neural network layers: receive a plurality of weight inputs and a plurality of activation inputs for the neural network layer, and generate a plurality of accumulated values based on the plurality of weight inputs and the plurality of activation inputs; and a vector computation unit communicatively coupled to the matrix computation unit and configured to, for each of the plurality of neural network layers: apply an activation function to each accumulated value generated by the matrix computation unit to generate a plurality of activated values for the neural network layer.

Neural Network Processor

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US Patent:
20160342891, Nov 24, 2016
Filed:
Sep 3, 2015
Appl. No.:
14/844524
Inventors:
- Mountain View CA, US
Norman Paul Jouppi - Palo Alto CA, US
Andrew Everett Phelps - Middleton WI, US
Reginald Clifford Young - Palo Alto CA, US
Thomas Norrie - Mountain View CA, US
Gregory Michael Thorson - Waunakee WI, US
Dan Luu - Madison WI, US
Assignee:
Google Inc. - Mountain View CA
International Classification:
G06N 3/08
G06N 99/00
Abstract:
A circuit for performing neural network computations for a neural network comprising a plurality of neural network layers, the circuit comprising: a matrix computation unit configured to, for each of the plurality of neural network layers: receive a plurality of weight inputs and a plurality of activation inputs for the neural network layer, and generate a plurality of accumulated values based on the plurality of weight inputs and the plurality of activation inputs; and a vector computation unit communicatively coupled to the matrix computation unit and configured to, for each of the plurality of neural network layers: apply an activation function to each accumulated value generated by the matrix computation unit to generate a plurality of activated values for the neural network layer.
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Dan Luu from San Jose, CA Get Report