Chun Yu Phones & Addresses
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1014 W Cameron Ave, West Covina, CA 91790 (626) 818-3420
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La Jolla, CA
Business Records
Name / Title
Company / Classification
Phones & Addresses
Owner
Daing Ki Sauna
Mfg Prefabricated Wood Buildings
Mfg Prefabricated Wood Buildings
4245 W 3 St, Los Angeles, CA 90020
President
America China International Culture Exchange Center
506 N Garfield Ave, Alhambra, CA 91801
1227 W Vly Blvd, Alhambra, CA 91803
1227 W Vly Blvd, Alhambra, CA 91803
Managing
Summit Alliance Holdings, LLC
General Merchandise
General Merchandise
661 Plateau Ave, Monterey Park, CA 91755
President
MING GUANG CORPORATION
1000 S Fremont Ave #1120, Alhambra, CA 91803
President
AMERICA SHENG LONG INTERNATIONAL INC
1015 E Las Tunas Dr, San Gabriel, CA 91776
904 N Monterey St, Alhambra, CA 91801
904 N Monterey St, Alhambra, CA 91801
President
CHINESE THERAPY CENTER INC
Health Practitioner's Office
Health Practitioner's Office
2054 Artesia Blvd #B, Torrance, CA 90504
2050 Artesia Blvd, Torrance, CA 90504
2050 Artesia Blvd, Torrance, CA 90504
President
JOY BEAUTY USA, INC
Beauty Shop
Beauty Shop
3224 W Olympic Bld STE 207, Los Angeles, CA 90006
3224 W Olympic Blvd, Los Angeles, CA 90006
3224 W Olympic Blvd, Los Angeles, CA 90006
Publications
Isbn (Books And Publications)
Little Green: Growing Up During the Chinese Cultural Revolution
View page
Author
Chun Yu
ISBN #
0689869436
Us Patents
Multi-Stage Floating-Point Accumulator
View pageUS Patent:
7543013, Jun 2, 2009
Filed:
Aug 18, 2006
Appl. No.:
11/506349
Inventors:
Yun Du - San Diego CA, US
Chun Yu - San Diego CA, US
Guofang Jiao - San Diego CA, US
Chun Yu - San Diego CA, US
Guofang Jiao - San Diego CA, US
Assignee:
QUALCOMM Incorporated - San Diego CA
International Classification:
G06F 7/38
US Classification:
708501
Abstract:
A multi-stage floating-point accumulator includes at least two stages and is capable of operating at higher speed. In one design, the floating-point accumulator includes first and second stages. The first stage includes three operand alignment units, two multiplexers, and three latches. The three operand alignment units operate on a current floating-point value, a prior floating-point value, and a prior accumulated value. A first multiplexer provides zero or the prior floating-point value to the second operand alignment unit. A second multiplexer provides zero or the prior accumulated value to the third operand alignment unit. The three latches couple to the three operand alignment units. The second stage includes a 3-operand adder to sum the operands generated by the three operand alignment units, a latch, and a post alignment unit.
On-Demand Multi-Thread Multimedia Processor
View pageUS Patent:
7685409, Mar 23, 2010
Filed:
Feb 21, 2007
Appl. No.:
11/677362
Inventors:
Yun Du - San Diego CA, US
Guofang Jiao - San Diego CA, US
Chun Yu - San Diego CA, US
Guofang Jiao - San Diego CA, US
Chun Yu - San Diego CA, US
Assignee:
QUALCOMM Incorporated - San Diego CA
International Classification:
G06F 9/00
US Classification:
712228
Abstract:
A device includes a multimedia processor that can concurrently support multiple applications for various types of multimedia such as graphics, audio, video, camera, games, etc. The multimedia processor includes configurable storage resources to store instructions, data, and state information for the applications and assignable processing units to perform various types of processing for the applications. The configurable storage resources may include an instruction cache to store instructions for the applications, register banks to store data for the applications, context registers to store state information for threads of the applications, etc. The processing units may include an arithmetic logic unit (ALU) core, an elementary function core, a logic core, a texture sampler, a load control unit, a flow controller, etc. The multimedia processor allocates a configurable portion of the storage resources to each application and dynamically assigns the processing units to the applications as requested by these applications.
Pixel Cache For 3D Graphics Circuitry
View pageUS Patent:
7737985, Jun 15, 2010
Filed:
Jan 8, 2007
Appl. No.:
11/621052
Inventors:
William Torzewski - San Diego CA, US
Chun Yu - San Diego CA, US
Alexei V. Bourd - San Diego CA, US
Chun Yu - San Diego CA, US
Alexei V. Bourd - San Diego CA, US
Assignee:
QUALCOMM Incorporated - San Diego CA
International Classification:
G09G 5/36
G06T 15/30
G06T 17/20
G06T 15/30
G06T 17/20
US Classification:
345557, 345423
Abstract:
Apparatus are provided including device memory, hardware entities, a sub-image cell value cache, and a cache write operator. At least some of the hardware entities perform actions involving access to and use of the device memory. The hardware entities include 3D graphics circuitry to process, for ready display, 3D images from primitive objects. The cache is separate from the device memory, and is provided to hold data, including buffered sub-image cell values. The cache is connected to the 3D graphics circuitry so that pixel processing portions of the 3D graphics circuitry access the buffered sub-image cell values in the cache, in lieu of the pixel processing portions directly accessing the sub-image cell values in the device memory. The write operator writes the buffered sub-image cell values to the device memory under direction of a priority scheme. The priority scheme preserves in the cache border cell values bordering one or more primitive objects.
Universal Rasterization Of Graphic Primitives
View pageUS Patent:
7791605, Sep 7, 2010
Filed:
May 1, 2007
Appl. No.:
11/742753
Inventors:
Guofang Jiao - San Diego CA, US
William Torzewski - San Diego CA, US
Chun Yu - San Diego CA, US
Brian Ruttenberg - Goleta CA, US
William Torzewski - San Diego CA, US
Chun Yu - San Diego CA, US
Brian Ruttenberg - Goleta CA, US
Assignee:
QUALCOMM Incorporated - San Diego CA
International Classification:
G06T 11/20
G09G 5/00
G09G 5/00
US Classification:
345441, 345620
Abstract:
A technique for universally rasterizing graphic primitives used in computer graphics is described. Configurations of the technique include determining three edges and a bounded region in a retrofitting bounding box. Each primitive has real and intrinsic edges. The process uses no more than three real edges of any one graphic primitive. In the case of a line, a third edge is set coincident with one of its two real edges. The area between the two real edges is enclosed by opposing perimeter edges of the bounding box. In the case of a rectangle, only three real edges are used. The fourth edge corresponds to a bounding edge provided by the retrofitting bounding box. In exemplary applications, the technique may be used in mobile video-enabled devices, such as cellular phones, video game consoles, PDAs, laptop computers, video-enabled MP3 players, and the like.
Relative Address Generation
View pageUS Patent:
7805589, Sep 28, 2010
Filed:
Aug 31, 2006
Appl. No.:
11/469347
Inventors:
Yun Du - San Diego CA, US
Chun Yu - San Diego CA, US
Guofang Jiao - San Diego CA, US
Chun Yu - San Diego CA, US
Guofang Jiao - San Diego CA, US
Assignee:
QUALCOMM Incorporated - San Diego CA
International Classification:
G06F 12/00
US Classification:
711220, 711202, 345545
Abstract:
Techniques to efficiently handle relative addressing are described. In one design, a processor includes an address generator and a storage unit. The address generator receives a relative address comprised of a base address and an offset, obtains a base value for the base address, sums the base value with the offset, and provides an absolute address corresponding to the relative address. The storage unit receives the base address and provides the base value to the address generator. The storage unit also receives the absolute address and provides data at this address. The address generator may derive the absolute address in a first clock cycle of a memory access. The storage unit may provide the data in a second clock cycle of the memory access. The storage unit may have multiple (e. g. , two) read ports to support concurrent address generation and data retrieval.
Graphics Processing Unit With Unified Vertex Cache And Shader Register File
View pageUS Patent:
7928990, Apr 19, 2011
Filed:
Sep 27, 2006
Appl. No.:
11/535809
Inventors:
Guofang Jiao - San Diego CA, US
Chun Yu - San Diego CA, US
Yun Du - San Diego CA, US
Chun Yu - San Diego CA, US
Yun Du - San Diego CA, US
Assignee:
Qualcomm Incorporated - San Diego CA
International Classification:
G09G 5/36
US Classification:
345557, 345559, 345606, 345426
Abstract:
Techniques are described for processing computerized images with a graphics processing unit (GPU) using a unified vertex cache and shader register file. The techniques include creating a shared shader coupled to the GPU pipeline and a unified vertex cache and shader register file coupled to the shared shader to substantially eliminate data movement within the GPU pipeline. The GPU pipeline sends image geometry information based on an image geometry for an image to the shared shader. The shared shader performs vertex shading to generate vertex coordinates and attributes of vertices in the image. The shared shader then stores the vertex attributes in the unified vertex cache and shader register file, and sends only the vertex coordinates of the vertices back to the GPU pipeline. The GPU pipeline processes the image based on the vertex coordinates, and the shared shader processes the image based on the vertex attributes.
Graphics System Employing Shape Buffer
View pageUS Patent:
7944442, May 17, 2011
Filed:
Dec 12, 2006
Appl. No.:
11/609762
Inventors:
Angus M. Dorbie - San Diego CA, US
Alexei V. Bourd - San Diego CA, US
Chun Yu - San Diego CA, US
Alexei V. Bourd - San Diego CA, US
Chun Yu - San Diego CA, US
Assignee:
Qualcomm Incorporated - San Diego CA
International Classification:
G06T 15/40
US Classification:
345421, 345611, 345613, 345614, 345622, 345626
Abstract:
The system includes a shape buffer manager configured to store coverage data in the shape buffer. The coverage data indicates whether each mask pixel is a covered pixel or an uncovered pixel. A mask pixel is a covered pixel when a shape to be rendered on a screen covers the mask pixel such that one or more coverage criteria is satisfied and is an uncovered pixel when the shape does not cover the mask pixel such that the one or more coverage criteria are satisfied. A bounds primitive rasterizer is configured to rasterize a bounds primitive that bounds the shape. The bounds primitive is rasterized into primitive pixels that each corresponds to one of the mask pixels. A pixel screener is configured to employ the coverage data from the shape buffer to screen the primitive pixels into retained pixels and discarded pixels. The retained pixels each corresponds to a mask pixel that the coverage data indicates is a covered pixel and the discarded pixels each correspond to a mask pixels that the coverage data indicates is an uncovered pixel. The system also includes an attribute generator configured to generate pixel attributes for the retained primitive pixels and also configured not to generate pixel attributes for the discarded primitive pixels.
Graphics Processing Unit With Extended Vertex Cache
View pageUS Patent:
7952588, May 31, 2011
Filed:
Aug 3, 2006
Appl. No.:
11/499187
Inventors:
Guofang Jiao - San Diego CA, US
Brian Evan Ruttenberg - Goleta CA, US
Chun Yu - San Diego CA, US
Yun Du - San Diego CA, US
Brian Evan Ruttenberg - Goleta CA, US
Chun Yu - San Diego CA, US
Yun Du - San Diego CA, US
Assignee:
Qualcomm Incorporated - San Diego CA
International Classification:
G06T 1/20
G06T 1/00
G09G 5/36
G06T 1/00
G09G 5/36
US Classification:
345557, 345506, 345522
Abstract:
Techniques are described for processing computerized images with a graphics processing unit (GPU) using an extended vertex cache. The techniques include creating an extended vertex cache coupled to a GPU pipeline to reduce an amount of data passing through the GPU pipeline. The GPU pipeline receives an image geometry for an image, and stores attributes for vertices within the image geometry in the extended vertex cache. The GPU pipeline only passes vertex coordinates that identify the vertices and vertex cache index values that indicate storage locations of the attributes for each of the vertices in the extended vertex cache to other processing stages along the GPU pipeline. The techniques described herein defer the setup of attribute gradients to just before attribute interpolation in the GPU pipeline. The vertex attributes may be retrieved from the extended vertex cache for attribute gradient setup just before attribute interpolation in the GPU pipeline.