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Chok W Ho

from San Jose, CA
Age ~64
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Also known as:
Chok W Jo, Ho Chok
Related to:
Anh Thi Ho, 85Ahn N HoJuliana S Ho, 67Stanley K Ho, 69Jeho LeeI WilhoyteWme WilhoyteRachel Lynn Ho, 43Kyoungah Lee, 57Antonio Reyes, 39Pattis WilhoytePatricia Wilhoyte, 75Susan Ho, 42S AWilliam E WilhoyteKin W Ho, 66Est WilhoyteKatheleen H WilhoyteKathelen H WilhoyteCathleen Wilhoyte
Connected to:
Adrianne Ho, 38Agnes P Ho, 92Aida Ho, 76Amy Ho, 44Angelina Ho, 43Anita Ho, 53Anne D Ho, 68Anya Ho, 35Baochau V Ho, 41Baotran T Ho, 38

Chok Ho Phones & Addresses

  • San Jose, CA
  • 3333 Vicente St, San Francisco, CA 94116
  • 2077 Ornellas Dr, Milpitas, CA 95035
  • 372 Meadowhaven Way, Milpitas, CA 95035
  • Fremont, CA

Resumes

Resumes

Chok Ho Photo 1

Chok Ho

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Location:
San Francisco, CA
Industry:
Semiconductors
Work:
Globalfoundries Apr 2015 - Sep 2017
Mts - Process
Qualcomm Nov 2006 - Nov 2012
Staff Engineer
Spatial Photonics Apr 2005 - Nov 2006
Senior Staff Engineer
Linear Technology Sep 2000 - Apr 2005
Senior Process Engineer
Lam Research Mar 1996 - Sep 2000
Staff Engineer
Education:
University of California, Berkeley 1983 - 1986
Bachelors, Bachelor of Science, Chemical Engineering
Skills:
Semiconductors
Mems
Plasma Etch
Thin Films
Design of Experiments
Spc
Failure Analysis
Process Integration
Yield
Fmea
Pecvd
Photolithography
Sensors
Cvd
Pvd
Characterization
R&D
Process Engineering
Jmp
Ic
Process Simulation
Silicon
Semiconductor Industry
Etching
Electronics
Cmos
Engineering Management
Product Engineering
Materials
R
Manufacturing
Physical Vapor Deposition
Research and Development
Metrology
Chok Ho Photo 2

Senior Staff Engineer

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Location:
San Francisco, CA
Industry:
Semiconductors
Work:
Spatial Photonics
Senior Staff Engineer
Chok Ho Photo 3

Chok Ho

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Location:
San Francisco Bay Area
Industry:
Semiconductors
Skills:
MEMS
Silicon
Characterization
JMP
Failure Analysis
Semiconductors
Thin Films
Design of Experiments
Process Engineering
Plasma Etch
PECVD
Chok Ho Photo 4

Chok Ho

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Publications

Us Patents

Use Of Hydrocarbon Addition For The Elimination Of Micromasking During Etching Of Organic Low-K Dielectrics

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US Patent:
6620733, Sep 16, 2003
Filed:
Feb 12, 2001
Appl. No.:
09/782437
Inventors:
Chok W. Ho - Milpitas CA
Assignee:
Lam Research Corporation - Fremont CA
International Classification:
H01L 21311
US Classification:
438700, 438694, 438710
Abstract:
A method for etching features in an integrated circuit wafer, the wafer incorporating at least one dielectric layer is provided. Generally, the wafer is disposed within a reaction chamber. An etchant gas comprising a hydrocarbon additive and an active etchant is flowed into the reaction chamber. A plasma is formed from the etchant gas within the reaction chamber. The feature is etched in at least a portion of the dielectric layer.

Post-Etch Photoresist Strip With O2 And Nh3 For Organosilicate Glass Low-K Dielectric Etch Applications

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US Patent:
6777344, Aug 17, 2004
Filed:
Feb 12, 2001
Appl. No.:
09/782678
Inventors:
Rao V. Annapragada - Union City CA
Ian J. Morey - Singapore, SG
Chok W. Ho - Milpitas CA
Assignee:
Lam Research Corporation - Fremont CA
International Classification:
H01L 21302
US Classification:
438725, 438723, 438710
Abstract:
Process for stripping photoresist from a semiconductor wafer formed with at least one layer of OSG dielectric. The stripping process may be formed in situ or ex situ with respect to other integrated circuit fabrication processes. The process includes a reaction may be oxidative or reductive in nature. The oxidative reaction utilizes an oxygen plasma. The reductive reaction utilizes an ammonia plasma. The process of the present invention results in faster ash rates with less damage to the OSG dielectric than previously known stripping methods.

Use Of Ammonia For Etching Organic Low-K Dielectrics

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US Patent:
6893969, May 17, 2005
Filed:
Feb 12, 2001
Appl. No.:
09/782446
Inventors:
Chok W. Ho - Milpitas CA, US
Kuo-Lung Tang - Hsin-Chu, TW
Chung-Ju Lee - Hsin-Chu, TW
Assignee:
Lam Research Corporation - Fremont CA
International Classification:
H01K021/302
US Classification:
438706, 438710, 438712, 438714, 438720, 216 67, 216 72
Abstract:
Method for etching organic low-k dielectric using ammonia, NH3, as an active etchant. Processes using ammonia results in at least double the etch rate of organic low-k dielectric materials than processes using N2/H2 chemistries, at similar process conditions. The difference is due to the much lower ionization potential of NH3 versus N2 in the process chemistry, which results in significantly higher plasma densities and etchant concentrations at similar process conditions.

Use Of Ammonia For Etching Organic Low-K Dielectrics

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US Patent:
7105454, Sep 12, 2006
Filed:
Jan 21, 2004
Appl. No.:
10/762969
Inventors:
Chok W. Ho - Milpitas CA, US
Kuo-Lung Tang - Hsin-Chu, TW
Chung-Ju Lee - Hsin-Chu, TW
Assignee:
Lam Research Corporation - Fremont CA
International Classification:
H01L 21/302
US Classification:
438717, 438706, 438710, 438723, 257513
Abstract:
Method for etching organic low-k dielectric using ammonia, NH3, as an active etchant. Processes using ammonia results in at least double the etch rate of organic low-k dielectric materials than processes using N2/H2 chemistries, at similar process conditions. The difference is due to the much lower ionization potential of NH3 versus N2 in the process chemistry, which results in significantly higher plasma densities and etchant concentrations at similar process conditions.

Etching Processes Used In Mems Production

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US Patent:
8308962, Nov 13, 2012
Filed:
Sep 12, 2008
Appl. No.:
12/210010
Inventors:
Philip Floyd - Redwood City CA, US
Chok Ho - Milpitas CA, US
Teruo Sasagawa - Los Gatos CA, US
Xiaoming Yan - Sunnyvale CA, US
Assignee:
QUALCOMM MEMS Technologies, Inc. - San Diego CA
International Classification:
H01B 13/00
US Classification:
216 13, 216 63, 359290, 359292, 1563451, 15634527, 15634529
Abstract:
The efficiency of an etching process may be increased in various ways, and the cost of an etching process may be decreased. Unused etchant may be isolated and recirculated during the etching process. Etching byproducts may be collected and removed from the etching system during the etching process. Components of the etchant may be isolated and used to general additional etchant. Either or both of the etchant or the layers being etched may also be optimized for a particular etching process.

Etching Processes Used In Mems Production

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US Patent:
20090071933, Mar 19, 2009
Filed:
Sep 12, 2008
Appl. No.:
12/210026
Inventors:
Philip Floyd - Redwood City CA, US
Evgeni Gousev - Saratoga CA, US
David Heald - Solvang CA, US
Ben Ward Hertzler - Los Gatos CA, US
Chok Ho - Milpitas CA, US
Teruo Sasagawa - Los Gatos CA, US
Xiaoming Yan - Sunnyvale CA, US
Todd Lyle Zion - San Jose CA, US
Assignee:
Qualcomm MEMS Technologies, Inc. - San Diego CA
International Classification:
B44C 1/22
C23F 1/08
US Classification:
216 13, 15634551
Abstract:
The efficiency of an etching process may be increased in various ways, and the cost of an etching process may be decreased. Unused etchant may be isolated and recirculated during the etching process. Etching byproducts may be collected and removed from the etching system during the etching process. Components of the etchant may be isolated and used to general additional etchant. Either or both of the etchant or the layers being etched may also be optimized for a particular etching process.

Sidewall Spacers Along Conductive Lines

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US Patent:
20130113810, May 9, 2013
Filed:
Nov 4, 2011
Appl. No.:
13/289935
Inventors:
Chok Wah Ho - Milpitas CA, US
Fan Zhong - Fremont CA, US
Assignee:
QUALCOMM MEMS Technologies, Inc. - San Diego CA
International Classification:
G06F 13/00
H01L 31/18
H05K 3/10
H01L 31/0232
US Classification:
345520, 257435, 438 69, 29846, 257E31127
Abstract:
Systems, methods and apparatus are provided for electromechanical systems devices having a sidewall spacer along at least one sidewall of a conductive line. An electromechanical systems device can include a sidewall spacer along at least one sidewall of a conductive line under a movable layer. The sidewall spacer can be sloped such that the sidewall spacer has a decreasing width away from a substrate under the movable layer. The conductive line can be configured to route an electrical signal to the electromechanical systems device. In some implementations, a black mask structure of an electromechanical systems device can include the conductive line.

Ultra-High Oxide To Photoresist Selective Etch Of High-Aspect-Ratio Openings In A Low-Pressure, High-Density Plasma

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US Patent:
6486070, Nov 26, 2002
Filed:
Sep 21, 2000
Appl. No.:
09/666762
Inventors:
Chok W. Ho - Milpitas CA
Fang-Ju Lin - Tainan, TW
Chuan-Kai Lo - Hsin-chu, TW
Assignee:
Lam Research Corporation - Fremont CA
International Classification:
H01L 21302
US Classification:
438706, 438710, 438712, 438714
Abstract:
An etch that provides a high oxide to photoresist selectivity in a low-pressure, high-density plasma is provided. An extremely high reverse RIE lag is achieved, wherein the etching of small high-aspect ratio openings is possible, but that of large openings is not. A high-density plasma is generated so that carbon monoxide (CO) is ionized to CO so that at least 1 sccm equivalent of CO is provided. Excited CO neutrals (CO*) are also present within the plasma. Fluorocarbon and hydrofluorocarbon gases are also provided. The excited CO neutrals scavenge free fluorine, near the wafer surface and in the large openings, increasing polymer deposition on the photoresist and in the large openings thus reduce or stop etching in those regions. Concurrently, CO is not hindered by diffusion limitation and is readily accelerated deep into the small openings by an applied electric potential; hence, providing oxygen atoms near the bottom of the small openings which help to remove polymer at the etch front and eliminates the propensity for etch stop.
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Chok W Ho from San Jose, CA, age ~64 Get Report