Chi Te Yuan

20210302491, Sep 30, 2021

Mar 8, 2021

17/195384

- Tokyo, JP
Chi Yuan - San Jose CA, US
Seth Craighead - San Jose CA, US

G01R 31/28

Presented embodiments facilitate efficient and effective flexible implementation of different types of testing procedures in a test system. In one embodiment, a flexible sideband support system comprises a load board, testing electronics coupled to the load board, a controller coupled to the testing electronics. The load board is configured to couple with a plurality of devices under test (DUTs), wherein the load board includes in-band testing ports and sideband testing ports. The testing electronics is configured to test the plurality of DUTs, wherein a portion of testing electronics are organized in sideband resource groups. The controller is configured to direct testing of the DUTs, wherein the controller is coupled to the testing electronics and the controller directs selective allocation of the testing electronics in the sideband resource groups to various testing operations of the DUTs. In one exemplary implementation, the controller directs a portion of sideband testing of a plurality of DUTs concurrently.

20210303429, Sep 30, 2021

Mar 5, 2021

17/193668

- Tokyo, JP
Chi Yuan - San Jose CA, US

G06F 11/27
G06F 12/02

Presented embodiments facilitate efficient and effective flexible implementation of different types of testing procedures in a test system. In one embodiment, a multiple-name-space testing system comprises a load board, testing electronics, and a namespace testing tracker. The load board is configured to couple with a plurality of devices under test (DUTs). The testing electronics are configured to test the plurality of DUTs, wherein the testing electronics are coupled to the load board. The controller is configured to direct testing of multiple-name-spaces across the plurality of DUTs at least in part in parallel. The controller can be coupled to the testing electronics. The namespace testing tracker is configured to track testing of the plurality of DUTs, including the testing of the multiple-name-spaces across the plurality of DUTs at least in part in parallel. In one embodiment, the DUTs are NVMe SSD devices.

20210278458, Sep 9, 2021

Mar 5, 2021

17/193749

- Tokyo, JP
Chi YUAN - San Jose CA, US
Linden HSU - San Jose CA, US

G01R 31/3177
G06F 9/54

A method for testing DUT comprises receiving instructions from a system controller at a tester board, wherein the tester board comprises an FPGA and the tester processor are coupled to the system controller, and wherein the tester processor is operable to coordinate testing of a device under test (DUT). The method further comprises generating commands and data for testing the DUT and routing signals associated with the commands and the data in the FPGA based on a type of the DUT. Also, the method comprises transmitting the signals over lanes corresponding to a particular set of pins on the DUT, wherein the particular set of pins depend on the type of the DUT.

20210125680, Apr 29, 2021

Jan 6, 2021

17/142989

- Tokyo, JP
Chi Albert YUAN - San Jose CA, US

G11C 29/38
G11C 29/14

An automated test equipment (ATE) system comprises a computer system comprising a system controller, wherein the system controller is communicatively coupled to a tester processor, wherein the system controller is operable to transmit instructions to the tester processor. The tester processor is operable to generate commands and data from the instructions for coordinating testing of a device under test (DUT), wherein the DUT supports an arbitrary sector size, and wherein software layers on the tester processor perform computations to be able control data flow between the tester processor and sectors of arbitrary size in the DUT.

20200200819, Jun 25, 2020

Dec 20, 2018

16/227389

- Tokyo, JP
Michael JONES - San Jose CA, US
Chi YUAN - San Jose CA, US

G01R 31/28
G01R 1/02

An automated test equipment (ATE) apparatus comprises a computer system comprising a system controller, wherein the system controller is communicatively coupled to a tester processor and an FPGA. The tester processor is operable to generate commands and data from instructions received from the system controller for coordinating testing of a device under test (DUT), wherein the DUT supports a plurality of non-standard sector sizes and a plurality of protection modes. The FPGA is communicatively coupled to the tester processor, wherein the FPGA comprises at least one hardware accelerator circuit operable to internally generate commands and data transparently from the tester processor for testing the DUT, and wherein the at least one hardware accelerator circuit is able to perform computations to calculate protection information associated with the plurality of protection modes and to generate repeatable test patterns sized to fit each of the plurality of non-standard sector sizes.

20200088790, Mar 19, 2020

Sep 18, 2018

16/134792

- Tokyo, JP
Chi YUAN - San Jose CA, US

G01R 31/317
G01R 31/28
G06F 13/16
G06F 13/42

A Built-in-Self-Test (BIST) centric Automatic Test Equipment (ATE) framework can include a host controller and one or more tester units. The host controller can be configured to receive one or more inputs to initiate testing of a plurality of Devices Under Test (DUTs). The one or more tester unit can include a plurality of Universal Asynchronous Receiver-Transmitters (UARTs) communication links. The UART communication links can be configured to send one or more commands for initiating and controlling a Built-in-Self-Test (BIST) in the plurality of DUTs. The UART communication links can also be configured to receive test output data of the BIST from the plurality of DUTs. The host controller can also be configured to output the test output data of the BIST.