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Chi P Lin

from Fremont, CA
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Also known as:
Chi Ping Lin, Chiping Lin
Connected to:
Abby C Lin, 44Ai H Lin, 74Aidi Lin, 31Alisa Y Lin, 47Alyssa Lin, 39Amy LinAndrea Lin, 51Angelia Lin, 29Angelica B Lin, 52Anhua A Lin, 51

Chi Lin Phones & Addresses

  • Fremont, CA
  • Malden, MA
  • 42054 Via San Luis Rey, Fremont, CA 94539

Work

Position: Food Preparation and Serving Related Occupations

Education

Degree: High school graduate or higher

Professional Records

License Records

Chi Taw Lin

License #:
DN15876 - Expired
Category:
DENTISTRY
Issued Date:
Nov 7, 1984
Renew Date:
Mar 31, 1990
Expiration Date:
Mar 31, 1990
Type:
Dentist

Chi Lin

License #:
23516 - Active
Category:
Medicine
Issued Date:
Nov 22, 2005
Effective Date:
Nov 22, 2005
Expiration Date:
Oct 1, 2018
Type:
Physician

Medicine Doctors

Chi Lin Photo 1

Chi Hsiung Lin

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Specialties:
Internal Medicine
Work:
Joseph C Lin MD
240 Williamson St STE 506, Elizabeth, NJ 07202
(908) 965-0234 (phone), (908) 965-1191 (fax)
Education:
Medical School
Kaohsiung (takau) Med Coll, Kaohsiung, Taiwan (385 01 Prior 1/71)
Graduated: 1976
Procedures:
Cardiac Stress Test
Arthrocentesis
Vaccine Administration
Conditions:
Abnormal Vaginal Bleeding
Acute Conjunctivitis
Acute Pharyngitis
Benign Prostatic Hypertrophy
Bronchial Asthma
Languages:
English
Spanish
Description:
Dr. Lin graduated from the Kaohsiung (takau) Med Coll, Kaohsiung, Taiwan (385 01 Prior 1/71) in 1976. He works in Elizabeth, NJ and specializes in Internal Medicine. Dr. Lin is affiliated with Trinitas Regional Medical Center Williamson St Campus.

Real Estate Brokers

Chi Lin Photo 2

Chi Chi Lin, San Jose CA

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Specialties:
Buyer's Agent
Listing Agent
Work:
Kico Lin Realty
262 E. Gish Road, San Jose, CA 95112
(214) 908-6248 (Office)

Business Records

Name / Title
Company / Classification
Phones & Addresses
Chi Lin
President
Lin & Wang, Inc
1117 Fillmore St, San Francisco, CA 94115
Chi Feng Lin
Director
AUDIOXPERTS INC
1930 Washington St, Auburndale, MA 02466
251 Harvard St, Brookline, MA 02446
Chi Wen Lin
V-COMMS EXPRESS, INC
Chi Fen Lin
President
Taisho Japanese Cuisine
Eating Place
PO Box 1015, San Mateo, CA 94403
2946 S Norfolk St, San Mateo, CA 94403
(650) 577-8988
Chi I. Lin
President
INNOVATIVE INFORMATION TECHNOLOGY, INC
3645 Grand Ave #304, Oakland, CA 94610
Chi Fen Lin
President
TAI SHO CORPORATION
2946 S Norfolk St, San Mateo, CA 94403

Publications

Us Patents

Photolithographic Process For Reducing Repeated Defects

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US Patent:
54828198, Jan 9, 1996
Filed:
Apr 4, 1994
Appl. No.:
8/223255
Inventors:
Eddy Tjhia - Sunnyvale CA
Chi Lin - Milpitas CA
Anjali Anagol-Subbarao - San Jose CA
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
G03F 720
US Classification:
430394
Abstract:
A photolithographic process for forming a lead frame pattern or other pattern is described. In the preferred embodiment, a mask approximately 12 inches by 12 inches contains two nearly identical patterns: a first lead frame pattern is provided on one half of the mask, and a second lead frame pattern, having features reduced by 0. 3 mil, is provided on the other half of the mask. The first pattern is positioned over a copper web having a layer of photoresist laminated on it, and ultraviolet light is transmitted through the first pattern. The photoresist is thus exposed by a first image formed by the first pattern. While the copper web remains stationary, the mask is moved perpendicular to the length of the copper web so that the second pattern now forms a second image overlying the photoresist pattern from the first image. The photoresist layer is then exposed by the second image. The two nearly identical patterns on the mask essentially double expose the photoresist except for a 0.

Resistive Memory

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US Patent:
20200111836, Apr 9, 2020
Filed:
Oct 3, 2019
Appl. No.:
16/591944
Inventors:
- Taichung City, TW
Chi Shun LIN - Fremont CA, US
International Classification:
H01L 27/24
H01L 23/528
H01L 23/522
H01L 45/00
G11C 13/00
Abstract:
The invention provides a resistive memory with better area efficiency without degrading reliability, which includes an array area, word lines, a local bit line, source lines, and a shared bit line. In the array area, memory cells are arranged in a matrix, and each memory cells includes a variable resistance element and an accessing transistor. The word lines extend in a row direction of the array area and are connected to the memory cells in the row direction. The local bit line extends in a column direction of the array area. The source lines extend in the column direction and are connected to first electrodes of the memory cells in the column direction. The shared bit line is connected to the local bit line. The shared bit line extends in the row direction and is connected to second electrodes of the memory cells in the row direction.
Control profile
Chi P Lin from Fremont, CA Get Report