Chi Chung Lee

6615229, Sep 2, 2003

Jun 29, 2000

09/605543

Narsing Vijayrao - Santa Clara CA
Chi Keung Lee - San Jose CA
Kumar Sudarshan - Fremont CA

Intel Corporation - Santa Clara CA

G06F 752

708629

The present invention relates to a new low-power, high performance multiplier circuit design, and more specifically to a partitioned multiplier implemented using a modified, symmetrical Wallace tree structure that enables the power to parts of the multiplier to be selectively turned on and off. A multiplier implemented using complementary pass-transistor logic (CPL) 3:2 carry save adders (CSAs) includes a left array with a first multiple of CPL CSAs, a right array with a second multiple of CPL CSAs, and a merge block coupled to the left array and the right array, such that the left and right arrays are not coupled to each other. The left and right arrays are configured to independently receive power, such that, each array can be turned on and off without affecting the other array. The merge block includes a third multiple of CPL CSAs and the merge block can be configured to output a result value of a multiplication operation.

6820106, Nov 16, 2004

Jun 27, 2000

09/604620

Narsing K. Vijayrao - Santa Clara CA
Chi Keung Lee - San Jose CA
Sudarshan Kumar - Fremont CA

Intel Corporation - Santa Clara CA

G06F 738

708497, 708501

A method and apparatus to increase the performance of a floating point multiplier accumulator (FMAC). The method comprises receiving three floating point numbers and computing a product of the first floating point number and the second floating point number and adding a third floating point number to produce a sum value and a carry value. A propagate value, a kill value and a generate value are then computed based on the sum value and the carry value. Simultaneously the sum value is added to the carry value to create a first result, the sum value is added to the carry value and incremented by one to create a second result, the sum value is added to the carry value and incremented by two to create a third result, and a decimal point position is determined. One of the first result, the second result and the third result is then selected responsive to a rounding mode and the decimal point position. The selected result is normalized based on the decimal point position.

7213249, May 1, 2007

Nov 30, 2001

09/997408

Elise Y. Tung Loo - Foster City CA, US
Chi Cheng Lee - Santa Clara CA, US
Sachin Agarwal - Sunnyvale CA, US

Oracle International Corporation - Redwood Shores CA

G06F 13/00

719330

Identity Servers issue and respond to requests for performing remote operations. A local Identity Server receives a request to perform a remote operation. The local Identity Server identifies and executes any required local operations. After completing the local operations, the local Identity Server forwards the remote request to a remote Identity Server, which executes the remote operation. An Identity Server includes a management service, management registry, and request handler. The management service identifies and issues remote request to other servers. The request handler receives remote requests from other servers. The management registry maintains an index of function modules for performing local operations.

8140724, Mar 20, 2012

Aug 18, 2009

12/543335

Tony Yoon - Cupertino CA, US
Chi Kong Lee - Fremont CA, US

Marvell International Ltd. - Hamilton

G06F 13/12
G06F 13/38
G06F 13/20

710 74, 710313

A hybrid controller and a method for coupling a plurality of host and memory devices with a hybrid controller are provided. In one embodiment, a hybrid controller may couple one or more host devices to one or more memory devices via multiple interface controllers, each interface controller configurable as a host or as a device. In one embodiment, interface controllers may have access to data across coupled devices as arbitrated by a buffer manager.

8185713, May 22, 2012

Sep 17, 2008

12/212636

Hyunsuk Shin - Santa Clara CA, US
Chi Kong Lee - Fremont CA, US
Tony Yoon - Cupertino CA, US

Marvell World Travel Ltd. - St. Michael

G06F 13/18

711167

A method and apparatus for controlling access to solid state memory devices which may allow maximum parallelism on accessing solid state memory devices with minimal interventions from firmware. To reduce the waste of host time, multiple flash memory devices may be connected to each channel. A job/descriptor architecture may be used to increase parallelism by allowing each memory device to operate separately. A job may be used to represent a read, write or erase operation. When firmware wants to assign a job to a device, it may issue a descriptor, which may contain information about the target channel, the target device, the type of operation, etc. The firmware may provide descriptors without waiting for a response from a memory device, and several jobs may be issued continuously to form a job queue. After the firmware finishes programming descriptors, a sequencer may handle the remaining work so that the firmware may concentrate on other tasks.

8296487, Oct 23, 2012

Mar 13, 2012

13/419040

Tony Yoon - Cupertino CA, US
Chi Kong Lee - Fremont CA, US

Marvell International Ltd. - Hamilton

G06F 13/12

710 74, 710313

A first storage controller includes a first memory controller, a first interface controller, and a second interface controller. The first memory controller is configured to control a connection between the first storage controller and a first storage device. The first interface controller is configured as a device, and is configured to control a connection between the first storage controller and a first host. The second interface controller is configurable to function as a host or a device. The second interface controller is configured to control a connection between the first storage controller and a secondary device, function as a host when the secondary device is a second storage controller, and function as a device when the secondary device is a second host.

8438356, May 7, 2013

Sep 29, 2008

12/241000

Tony Yoon - Cupertino CA, US
Akio Goto - Saitama, JP
Chi Kong Lee - Fremont CA, US
Masayuki Urabe - Isehara, JP

Marvell World Trade Ltd. - St. Michael

G06F 12/00

711167, 711100, 711102, 711103, 711154, 711169

Methods, systems and computer program products for implementing a polling process among one or more flash memory devices are described. In some implementations, the polling process may include sending a read status command to a flash memory device to detect the ready or busy state of the flash memory device. A status register may be included in the flash memory device for storing a status signal indicating an execution state of a write (or erase) operation. A solid state drive system may perform the polling process by reading the status register of the flash memory device.

8500339, Aug 6, 2013

Jan 11, 2011

13/004874

Chi K. Lee - Palo Alto CA, US

Avago Technologies General IP (Singapore) Pte. Ltd. - Singapore

G02B 6/36

385 53, 385 88

A locking device is provided that is configured to be attached to the MPO connector module and placed in a locking state that prevents the MPO connector module from being decoupled from the receptacle. The locking device may be a locking clip that is configured to be inserted into a keying slot formed in an MPO connector module. When the locking clip is inserted into the keying slot and placed in a locking state, the locking clip prevents the MPO connector module from being decoupled from the receptacle. If the locking clip is placed in an unlocking state, a tool or fingers can be used to extract the locking clip from the keying slot, thereby making it possible to decouple the MPO connector module from the receptacle.