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Chao H Liu

from Atlanta, GA
Age ~86
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Also known as:
Chao K Liu, Han Liu Chao, Chaohan Liu
Related to:
Brian P Harrington, 69Wei Liu, 56Jianan Liu, 39Richard Y Hegg, 52Robert C Liu, 54Alice C Liu, 56Tsuei Chu LiuJie Liu Yanjie, 59
Connected to:
Adela Liu, 73Alec X Liu, 38Alpha T Liu, 46Amon Y Liu, 58Andrea Y Liu, 46Anqi Liu, 39Arden K Liu, 64Ba S Liu, 62Bailu Liu, 35Ban Liu, 48

Chao Liu Phones & Addresses

  • Atlanta, GA
  • 2406 Burlison Dr, Urbana, IL 61801 (217) 325-1347
  • San Francisco, CA
  • Stanford, CA
  • Mountain View, CA
  • San Jose, CA

Resumes

Resumes

Chao Liu Photo 1

Chao Liu Sunnyvale, CA

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Work:
Advenira Enterprises

Feb 2012 to 2000
Senior Scientist
Nanosys Inc
Palo Alto, CA
Jul 2004 to Feb 2012
R&D Scientist
Seagate Technology
Pittsburgh, PA
May 2001 to Jul 2004
Post Doctor Researcher & Research Staff Member
Georgia Institute of Technology
Atlanta, GA
Jan 1997 to May 2001
Graduate Research Assistant
Shanghai Institute of Optics and Fine Mechanics

Jul 1993 to Dec 1996
Chinese Academy of Sciences, Research Scientist
Education:
Georgia Institute of Technology
1997 to 2001
Ph.D. in Chemistry
University of Science and Technology of China
1988 to 1993
B.S. in Chemistry
Skills:
problem solving, failure analysis, TEM, SEM, nanotechnology, coating
Chao Liu Photo 2

Chao Liu Rego Park, NY

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Work:
Shenyin Wanguo Asset Management (Asia) Ltd., Central
Hong Kong, Hong Kong Island
Feb 2012 to Jun 2012
Asset Management Intern
Washington Mutual/JP Morgan Chase
Cupertino, CA
Sep 2008 to Dec 2008
Bank Teller
Vertical Marine Fighter Attack Squadron
San Diego, CA
Apr 2007 to Sep 2008
Production, Planning and Expediting Manager
Marine Aircraft Group
San Diego, CA
May 2005 to Apr 2007
Pre-Expended Branch Manager
Education:
FORDHAM UNIVERSITY
New York, NY
Feb 2012
B.A. in Leadership
Chao Liu Photo 3

Chao Liu Buffalo, NY

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Work:
Cisco System Inc
Santa Clara, CA
May 2011 to Aug 2011
Intern
SAP

Jan 2010 to May 2010
Intern
PwC

Jun 2009 to Jan 2010
(PricewaterhouseCoopers) Intern Shanghai, China
Education:
Tongji University
Jun 2010
Bachelor of Science in Software Engineering
State University of New State at Buffalo
Buffalo, NY
Master of Science in Computer Science and Engineering

Business Records

Name / Title
Company / Classification
Phones & Addresses
Chao Liu
President
Six Dynasties, Inc
Nonclassifiable Establishments
559 Pilgrim Dr, San Mateo, CA 94404
(650) 638-0886
Chao Liu
President
WANLU DEVELOPMENT CORPORATION
Metals Service Center
1400 Coleman Ave SUITE E15F, Santa Clara, CA 95050
271 N 1 St, San Jose, CA 95113
Chao Tung Liu
President
CADONA INTERNATIONAL, INC
PO Box 81, Fremont, CA 94537
Chao Jie Liu
Secretary
YOUNGS MEDICAL & HEALTHCARE ASSOCIATES, PC
6244 Crooked Crk Rd SUITE B, Norcross, GA 30092
343 Ashleigh Walk Pkwy, Suwanee, GA 30024
Chao Heng Liu
U.S. Daden Culture LLC
Book Publishing · Book Publishing Company · Beauty Shop
3440 Foothill Blvd, Oakland, CA 94601
3400 Eden Ln, Oakland, CA 94601
Chao Tung Liu
President
CADONA, INC
Whol Gifts · Other Miscellaneous Nondurable Goods Merchant Wholesalers
33401 Central Ave, Union City, CA 94587
Union City, CA 94587
(510) 429-1828
Chao Tung Liu
President
TONY & LINDA LIU'S FAMILY FOUNDATION
33401 Central Ave, Union City, CA 94587
Chao Liu
Liuchao, LLC
559 Pilgrim Dr, San Mateo, CA 94404
136 Barbaree Way, Tiburon, CA 94920

Publications

Isbn (Books And Publications)

Chinese New Year's Dragon

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Author

Chao Wei Liu

ISBN #

0671886029

Us Patents

Digital Current Share Bus Interface

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US Patent:
7772821, Aug 10, 2010
Filed:
Jun 12, 2007
Appl. No.:
11/818093
Inventors:
Chao Liu - San Jose CA, US
Anthonius Bakker - Morgan Hill CA, US
Assignee:
Analog Devices, Inc. - Norwood MA
International Classification:
G05F 1/00
US Classification:
323283
Abstract:
A digital current share bus interface connects to a power module which provides a signal representative of its output current, and adjusts the module's output current in response to a control signal received from the interface. A data formatting module receives the output current signal and generates a digital word that varies with the current; the bits of the word are coupled to a current share bus. A comparator module receives digital words conveyed via the bus and generated by the data formatting module at respective inputs, and provides the control signal to the power module so as to adjust its output current to match the current value represented by the digital word on the bus. In a typical implementation, multiple power modules are coupled to the current share bus via respective interfaces, with the output currents of all the power modules connected in parallel.

Methods And Devices For Forming Nanostructure Monolayers And Devices Including Such Monolayers

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US Patent:
7776758, Aug 17, 2010
Filed:
Jul 28, 2006
Appl. No.:
11/495188
Inventors:
Xiangfeng Duan - Mountain View CA, US
Chao Liu - San Jose CA, US
Assignee:
Nanosys, Inc. - Palo Alto CA
International Classification:
H01L 21/31
US Classification:
438758, 438128, 438507, 438509, 977891, 257E21209
Abstract:
Methods for forming or patterning nanostructure arrays are provided. The methods involve formation of arrays on coatings comprising nanostructure association groups, formation of arrays in spin-on-dielectrics, solvent annealing after nanostructure deposition, patterning using resist, and/or use of devices that facilitate array formation. Related devices for forming nanostructure arrays are also provided, as are devices including nanostructure arrays (e. g. , memory devices).

Methods And Devices For Forming Nanostructure Monolayers And Devices Including Such Monolayers

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US Patent:
7968273, Jun 28, 2011
Filed:
Jul 27, 2007
Appl. No.:
11/881739
Inventors:
Jian Chen - Mountain View CA, US
Xiangfeng Duan - Mountain View CA, US
Chao Liu - San Jose CA, US
Madhuri L. Nallabolu - Sunnyvale CA, US
J. Wallace Parce - Palo Alto CA, US
Srikanth Ranganathan - Mountain View CA, US
Assignee:
Nanosys, Inc. - Palo Alto CA
International Classification:
G03F 7/26
US Classification:
430311, 430328, 430394, 430330
Abstract:
Methods for forming or patterning nanostructure arrays are provided. The methods involve formation of arrays on coatings comprising nanostructure association groups, formation of arrays in spin-on-dielectrics, solvent annealing after nanostructure deposition, patterning using resist, and/or use of devices that facilitate array formation. Related devices for forming nanostructure arrays are also provided, as are devices including nanostructure arrays (e. g. , memory devices). Methods for protecting nanostructures from fusion during high temperature processing are also provided.

Electronic Grade Metal Nanostructures

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US Patent:
7976646, Jul 12, 2011
Filed:
Aug 18, 2006
Appl. No.:
11/506769
Inventors:
Srikanth Ranganathan - Mountain View CA, US
Paul Bernatis - Sunnyvale CA, US
Joel Gamoras - Vallejo CA, US
Chao Liu - San Jose CA, US
J. Wallace Parce - Palo Alto CA, US
Assignee:
Nanosys, Inc. - Palo Alto CA
International Classification:
C22C 5/04
B32B 15/02
US Classification:
148430, 420462, 428546
Abstract:
Methods for producing electronic grade metal nanostructures having low levels of contaminants are provided. Monolayer arrays, populations, and devices including such electronic grade nanostructures are described. In addition, novel methods and compositions for production of Group 10 metal nanostructures and for production of ruthenium nanostructures are provided, along with methods for recovering nanostructures from suspension.

Methods And Devices For Forming Nanostructure Monolayers And Devices Including Such Monolayers

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US Patent:
8507390, Aug 13, 2013
Filed:
Jun 29, 2010
Appl. No.:
12/803568
Inventors:
Jian Chen - Sunnyvale CA, US
Karen Chu Cruden - Pleasanton CA, US
Xiangfeng Duan - Mountain View CA, US
Chao Liu - San Jose CA, US
J. Wallace Parce - Palo Alto CA, US
Assignee:
Sandisk Corporation - Milpitas CA
International Classification:
H01L 21/3105
US Classification:
438782, 438128, 438674, 977845, 977855, 257E21241
Abstract:
Methods for forming or patterning nanostructure arrays are provided. The methods involve formation of arrays on coatings comprising nanostructure association groups, formation of arrays in spin-on-dielectrics, solvent annealing after nanostructure deposition, patterning using resist, and/or use of devices that facilitate array formation. Related devices for forming nanostructure arrays are also provided, as are devices including nanostructure arrays (e. g. , memory devices).

Methods And Devices For Forming Nanostructure Monolayers And Devices Including Such Monolayers

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US Patent:
8558304, Oct 15, 2013
Filed:
Apr 29, 2011
Appl. No.:
13/098082
Inventors:
Jian Chen - Sunnyvale CA, US
Xiangfeng Duan - Los Angeles CA, US
Chao Liu - San Jose CA, US
Madhuri Nallabolu - Sunnyvale CA, US
J. Wallace Parce - Palo Alto CA, US
Srikanth Ranganathan - Mountain View CA, US
Assignee:
SanDisk Corporation - Milpitas CA
International Classification:
H01L 29/792
US Classification:
257325, 257314, 257315, 257406, 257E29039, 438311, 438507, 438509, 438128, 977891
Abstract:
Methods for forming or patterning nanostructure arrays are provided. The methods involve formation of arrays on coatings comprising nanostructure association groups, formation of arrays in spin-on-dielectrics, solvent annealing after nanostructure deposition, patterning using resist, and/or use of devices that facilitate array formation. Related devices for forming nanostructure arrays are also provided, as are devices including nanostructure arrays (e. g. , memory devices). Methods for protecting nanostructures from fusion during high temperature processing are also provided.

Post-Deposition Encapsulation Of Nanostructures: Compositions, Devices And Systems Incorporating Same

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US Patent:
20060040103, Feb 23, 2006
Filed:
Jun 7, 2005
Appl. No.:
11/147670
Inventors:
Jeffery Whiteford - Belmont CA, US
Rhett Brewer - Sunnyvale CA, US
Mihai Buretea - San Francisco CA, US
Jian Chen - Mountain View CA, US
Karen Cruden - Pleasanton CA, US
Xiangfeng Duan - Mountain View CA, US
William Freeman - San Mateo CA, US
David Heald - Solvang CA, US
Francisco Leon - Palo Alto CA, US
Chao Liu - San Jose CA, US
Andreas Meisel - San Francisco CA, US
Kyu Min - San Jose CA, US
J. Parce - Palo Alto CA, US
Erik Scher - San Francisco CA, US
Assignee:
NANOSYS, Inc. - Palo Alto CA
International Classification:
B32B 5/16
US Classification:
428403000
Abstract:
Ligand compositions for use in preparing discrete coated nanostructures are provided, as well as the coated nanostructures themselves and devices incorporating same. Methods for post-deposition shell formation on a nanostructure and for reversibly modifying nanostructures are also provided. The ligands and coated nanostructures of the present invention are particularly useful for close packed nanostructure compositions, which can have improved quantum confinement and/or reduced cross-talk between nanostructures.

Post-Deposition Encapsulation Of Nanostructures: Compositions, Devices And Systems Incorporating Same

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US Patent:
20080032134, Feb 7, 2008
Filed:
Feb 13, 2007
Appl. No.:
11/706730
Inventors:
Jeffery Whiteford - Belmont CA, US
Rhett Brewer - Sunnyvale CA, US
Mihai Buretea - San Francisco CA, US
Jian Chen - Mountain View CA, US
Karen Cruden - Pleasanton CA, US
Xiangfeng Duan - Mountain View CA, US
William Freeman - San Mateo CA, US
David Heald - Solvang CA, US
Francisco Leon - Palo Alto CA, US
Chao Liu - San Jose CA, US
Andreas Meisel - San Francisco CA, US
Kyu Min - San Jose CA, US
J. Parce - Palo Alto CA, US
Erik Scher - San Francisco CA, US
Assignee:
NANOSYS, Inc. - Palo Alto CA
International Classification:
B32B 5/16
B32B 15/04
B32B 17/06
US Classification:
428402240
Abstract:
Ligand compositions for use in preparing discrete coated nanostructures are provided, as well as the coated nanostructures themselves and devices incorporating same. Methods for post-deposition shell formation on a nanostructure and for reversibly modifying nanostructures are also provided. The ligands and coated nanostructures of the present invention are particularly useful for close packed nanostructure compositions, which can have improved quantum confinement and/or reduced cross-talk between nanostructures.
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Chao H Liu from Atlanta, GA, age ~86 Get Report