Byong Oh Phones & Addresses
-
Los Angeles, CA
-
Elmhurst, NY
-
Laton, CA
Publications
Us Patents
Systems And Methods For Fabrication Of Superconducting Integrated Circuits
View pageUS Patent:
20110089405, Apr 21, 2011
Filed:
Feb 25, 2010
Appl. No.:
12/992049
Inventors:
Eric Ladizinsky - Manhattan Beach CA, US
Geordie Rose - Burnaby, CA
Jeremy P. Hilton - Burnaby, CA
Eugene Dantsker - San Diego CA, US
Byong Hyop Oh - San Jose CA, US
Geordie Rose - Burnaby, CA
Jeremy P. Hilton - Burnaby, CA
Eugene Dantsker - San Diego CA, US
Byong Hyop Oh - San Jose CA, US
Assignee:
D-WAVE SYSTEMS INC. - Burnaby BC
International Classification:
H01L 39/22
H01L 39/24
H01L 39/24
US Classification:
257 31, 438 2, 257E39014
Abstract:
Various techniques and apparatus permit fabrication of superconductive circuits and structures, for instance Josephson junctions, which may, for example be useful in quantum computers. For instance, a low magnetic flux noise trilayer structure may be fabricated having a dielectric structure or layer interposed between two elements or layers capable of superconducting. A superconducting via may directly overlie a Josephson junction. A structure, for instance a Josephson junction, may be carried on a planarized dielectric layer. A fin may be employed to remove heat from the structure. A via capable of superconducting may have a width that is less than about 1 micrometer. The structure may be coupled to a resistor, for example by vias and/or a strap connector.
Method Of Forming Superconducting Wiring Layers With Low Magnetic Noise
View pageUS Patent:
20180219150, Aug 2, 2018
Filed:
Aug 12, 2015
Appl. No.:
15/503367
Inventors:
- Burnaby, CA
Eric G. Ladizinsky - Manhattan Beach CA, US
J. Jason Yao - San Ramon CA, US
Byong Hyop Oh - San Jose CA, US
Eric G. Ladizinsky - Manhattan Beach CA, US
J. Jason Yao - San Ramon CA, US
Byong Hyop Oh - San Jose CA, US
International Classification:
H01L 39/24
H01L 39/22
H01L 21/768
H01L 39/22
H01L 21/768
Abstract:
Fabricating wiring layers above a Josephson junction multi-layer may include removing a part of the multilayer; depositing an insulating layer to overlie a part of the multilayer; and patterning the insulating layer to define a hole in the insulating layer. The method includes depositing a first superconducting wiring layer over a part of the insulating layer and within a portion of the hole. Further, insulating and wiring layers may be deposited and a topmost wiring layer defined. The method includes depositing a passivating layer to overlie the topmost wiring layer. Fabricating a superconducting integrated circuit comprising a hybrid dielectric system may include depositing a high-quality dielectric layer that overlies a superconducting feature. The method includes depositing a second dielectric layer that overlies at least part of the high-quality dielectric layer. The second dielectric layer can comprise a conventional dielectric material.