Bo O Wang

6377071, Apr 23, 2002

Mar 31, 2000

09/540292

Bo Wang - Fremont CA
Pidugu L. Narayana - Sunnyvale CA

Cypress Semiconductor Corp. - San Jose CA

H03K 19173

326 46, 326 12, 326 96, 365220, 365221

An apparatus comprising a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate (i) one or more first enable signals and (ii) one or more first flag signals in response to a first clock signal and a second enable signal. The second circuit may be configured to generate a second flag signal in response to (i) the one or more first enable signals, (ii) the one or more first control signals, (iii) a second clock signal, and (iv) a pulse signal. The third circuit may be configured to generate the pulse signal in response to (i) a third clock signal and (ii) the one or more first flag signals.

7724596, May 25, 2010

Sep 12, 2008

12/209577

Pantas Sutardja - Los Gatos CA, US
Yonghua Song - Cupertino CA, US
Bo Wang - Sunnyvale CA, US
Chih-Hsin Wang - San Jose CA, US
Qiang Tang - Cupertino CA, US

Marvell World Trade Ltd. - St. Michael

G11C 7/02
H03F 3/45

365208, 365207, 327 51, 327 56

A sensing amplifier for a memory cell comprises a selection stage that outputs one of a reference current and a memory cell current during a first period and the other of the reference current and the memory cell current during a second period. The first period and the second period are non-overlapping. An input stage generates a first current based on the one of the reference current and the memory cell current during the first period and generates a second current based on the other of the reference current and the memory cell current during the second period. A sensing stage senses a first value based on the first current and stores the first value during the first period, senses a second value based on the second current during the second period and compares the first value to the second value.

7746704, Jun 29, 2010

Sep 12, 2008

12/209794

Qiang Tang - Cupertino CA, US
Bo Wang - Sunnyvale CA, US
Chih-Hsin Wang - San Jose CA, US

Marvell International Ltd. - Hamilton

G11C 16/04

36518528, 36518503, 36518518

A system includes an input that receives a control signal and a program module that initializes a nonvolatile multilevel memory cell based on the control signal. The program module initializes the nonvolatile multilevel memory cell by programming the nonvolatile multilevel memory cell to one of S states of the nonvolatile multilevel memory cell, where S is an integer greater than 1. The one of the S states is different than a lowest one of the S states.

7791406, Sep 7, 2010

Jan 11, 2007

11/652907

Bo Wang - Sunnyvale CA, US
Yonghua Song - Cupertino CA, US

Marvell International Ltd.

G05F 1/46

327544, 326 34

A low leakage power management system is provided. An external voltage domain is selectively coupled to the internal voltage domain of an integrated circuit according to demand for the functions provided by the integrated circuit. An external voltage Vis connected to the internal supply voltage plane of the integrated circuit when the integrated circuit is active. The external supply voltage Vis disconnected from the integrated circuit chip during idle periods. A plurality of switch cells may be provided for connecting the external voltage Vto the integrated circuit. A multi-step sequence is provided for connecting the external supply voltage Vto the chip's internal supply voltage plane to prevent excessive current from flowing through any individual switch cell.

7856048, Dec 21, 2010

Nov 19, 2007

11/942473

Lydi Smaini - St. Julien en Genevois, FR
Neric Fong - Sunnyvale CA, US
Sang Won Son - Sunnyvale CA, US
Bo Wang - Sunnyvale CA, US

Marvell International, Ltd. - Hamilton

H04B 1/38

375221, 375296, 375346, 375261, 375270, 455 47, 455109, 4551152, 455 6716, 4551143, 4551271, 455126, 455 6711, 330 2

The disclosure can provide methods and systems for autocalibrating a transceiver. The method can include upconverting a bandpass input signal by mixing the bandpass input signal with a first local oscillator signal to form an initial transmitter signal. The initial transmitter signal can be looped back to a receiver and downconverted with a second local oscillator signal having a frequency that is different from the first local oscillator to form an intermediate frequency signal. At least one of a gain and a phase of the transmitter can be adjusted based on a transmitter image sideband of the intermediate frequency signal to generate a calibrated transmitter signal having minimized transmitter image sideband.

7948810, May 24, 2011

Oct 13, 2008

12/250021

Qiang Tang - Cupertino CA, US
Bo Wang - Sunnyvale CA, US
Chih-Hsin Wang - San Jose CA, US

Marvell International Ltd. - Hamilton

G11C 7/00

36518911, 36518912, 36518907

A level shifter includes a level shifter module that receives a first input signal having high and low states and at least one voltage supply signal, and that generates a latch control signal based on the high and low states of the first input signal. A latch module receives the latch control signal, a data input signal, and the at least one voltage supply signal. The latch module selectively stores data associated with the data input signal based on the latch control signal. The latch module selectively changes the at least one voltage supply signal from a first level to a second level and outputs the data according to the second level based on the latch control signal.

8004352, Aug 23, 2011

Sep 1, 2010

12/873997

Bo Wang - Sunnyvale CA, US
Younghua Song - Cupertino CA, US

Marvell International Ltd.

G05F 1/10

327544, 326 34

A low leakage power management system is provided. An external voltage domain is selectively coupled to the internal voltage domain of an integrated circuit according to demand for the functions provided by the integrated circuit. An external voltage Vis connected to the internal supply voltage plane of the integrated circuit when the integrated circuit is active. The external supply voltage Vis disconnected from the integrated circuit chip during idle periods. A plurality of switch cells may be provided for connecting the external voltage Vto the integrated circuit. A multi-step sequence is provided for connecting the external supply voltage Vto the chip's internal supply voltage plane to prevent excessive current from flowing through any individual switch cell.

8248156, Aug 21, 2012

Aug 19, 2011

13/213695

Bo Wang - Sunnyvale CA, US
Younghua Song - Cupertino CA, US

Marvell International Ltd.

G05F 1/46

327544, 326 34

A low leakage power management system is provided. An external voltage domain is selectively coupled to the internal voltage domain of an integrated circuit according to demand for the functions provided by the integrated circuit. An external voltage Vis connected to the internal supply voltage plane of the integrated circuit when the integrated circuit is active. The external supply voltage Vis disconnected from the integrated circuit chip during idle periods. A plurality of switch cells may be provided for connecting the external voltage Vto the integrated circuit. A multi-step sequence is provided for connecting the external supply voltage Vto the chip's internal supply voltage plane to prevent excessive current from flowing through any individual switch cell.