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Bo Living Lu

from San Diego, CA
Age ~53
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Also known as:
Bo O Lu, Bo Lu Li, Lu Lu, Lu Bo
Related to:
Hui Li, 56Qiang Zhang, 54John LeeXiuling Li, 60Muchen Li, 76Qing LiMengchen Yu, 53Wei He, 66Guisheng Li, 95Sam T Lee, 81X LiaaronMichael Z Lee, 45Dan Lu, 49Yuzeng LuShenge Yu, 80Xintian E Lin, 55Wei Li, 64Grace W Lee, 82Chi Y LuXiuling Li, 53Aaron X Lee, 48
Connected to:
Abigail I Lu, 32Aiping Lu, 54Allen C Lu, 46Anjian Lu, 84Anna G Lu, 67Anne B Lu, 72Arnold W Lu, 49Ava Lu, 36Ay K Lu, 54Barbara T Lu, 74

Bo Lu Phones & Addresses

  • San Diego, CA
  • Mc Kinney, TX
  • 20230 Suncoast Dr, Katy, TX 77449
  • Tomball, TX
  • Hillsboro, OR
  • Irvine, CA
  • Carlsbad, CA
  • Baton Rouge, LA
  • Little Elm, TX
  • Gonzales, LA
  • Zachary, LA

Work

Company: Ryz, portland, usa Aug 2013 Position: Logistic and market consultant

Education

School / High School: Portland State University- Portland, OR Sep 2012 Specialities: MBA in Supply Chain Management and Marketing

Skills

Chinese • Japanese • Marketing • Supply Chain Management

Specialities

Buyer's Agent • Listing Agent

Resumes

Resumes

Bo Lu Photo 1

Bo Lu Portland, OR

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Work:
RYZ, Portland, USA

Aug 2013 to 2000
Logistic and Market Consultant
Business Capstone
Hillsboro, OR
Jul 2013 to Dec 2013
Marketing Consultant
Darun Food Co., LTD
Shenyang, CN
Jan 2011 to Aug 2011
Market Consultant
Dalian Jiahe Foreign Languages Training School
Dalian, CN
Mar 2010 to Dec 2010
Language Trainer - Internship
Dalian University of Foreign Languages
Dalian, Liaoning
Sep 2009 to Jun 2010
Chairman of Student Sports Association
IBM Summer Training Program

Jul 2009 to Sep 2009
Internship
Education:
Portland State University
Portland, OR
Sep 2012 to 2000
MBA in Supply Chain Management and Marketing
Dalian University of Foreign Languages
Dalian, CN
Sep 2007 to Jun 2011
Bachelor of Management in Japanese and Marketing
Volleyball Team in Dalian University of Foreign Languages
2009 to 2011
Won the Champion in Liaoning Province
Certificate of Accounting Professional
Skills:
Chinese, Japanese, Marketing, Supply Chain Management

Business Records

Name / Title
Company / Classification
Phones & Addresses
Bo Lu
International News 8192
Convenience Stores
216, 414 3 Street SW, Calgary, AB T2P 1R2
(587) 999-9901
Bo Lu
International News 8192
Convenience Stores
(587) 999-9901
Bo Lu
Organizer
Blue Dolphin Software LC

Publications

Us Patents

Fiducials For Use In Registration Of A Patterned Surface

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US Patent:
20220414853, Dec 29, 2022
Filed:
Jun 21, 2022
Appl. No.:
17/845519
Inventors:
- San Diego CA, US
Robert Langlois - San Diego CA, US
Bo Lu - San Diego CA, US
International Classification:
G06T 7/00
G01N 15/14
G06T 3/00
G06T 7/30
Abstract:
Registration of a patterned flow cell may utilize fiducials comprising sets or groupings of features (e.g., sites, sample wells, nanowells) having known locations and in which the placement of the features is not in accordance with a periodic pattern or is otherwise distinguishable from the periodic pattern of sites present in non-fiducial regions of the flow cell substrate. In certain embodiments the positioning of the sites that are part of the fiducial represent a break or discontinuity in the periodic pattern of sites that are otherwise present on the surface of a patterned flow cell.

Using Non-Redundant Components To Increase Calculation Efficiency For Structured Illumination Microscopy

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US Patent:
20220283418, Sep 8, 2022
Filed:
May 20, 2022
Appl. No.:
17/750149
Inventors:
- San Diego CA, US
Andrew James YOUNG - San Diego CA, US
Andrew Dodge HEIBERG - San Diego CA, US
Bo LU - San Diego CA, US
Assignee:
Illumina, Inc. - San Diego CA
International Classification:
G02B 21/00
G02B 27/60
G01N 21/64
G06T 3/40
G02B 21/14
G06T 5/50
Abstract:
The technology disclosed present systems and methods to produce an enhanced resolution image from images of a target using structured illumination microscopy (SIM). The method includes transforming at least three images of the target captured by a sensor in a spatial domain into a Fourier domain to produce at least three frequency domain matrices that each include first blocks of complex coefficients and redundant second blocks of complex coefficients that are conjugates to the first blocks. The method includes reducing computing resources required to produce the enhanced resolution image by using first blocks of complex coefficients to produce at least three phase-separated half-matrices in the Fourier domain. The method includes performing one or more intermediate transformation on the phase-separated half-matrices to produce realigned shifted half-matrices. The method includes calculating complex coefficients of second blocks in the Fourier domain to produce full matrices from half-matrices.

Intensity Extraction And Spatial Crosstalk Attenuation For Base Calling

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US Patent:
20230015945, Jan 19, 2023
Filed:
Sep 2, 2022
Appl. No.:
17/902630
Inventors:
- San Diego CA, US
Eric Jon OJARD - San Francisco CA, US
Rami MEHIO - San Diego CA, US
Gavin Derek PARNABY - Laguna Niguel CA, US
Nitin UDPA - San Diego CA, US
Bo LU - San Diego CA, US
John S. VIECELI - Encinitas CA, US
Assignee:
ILLUMINA SOFTWARE, INC. - San Diego CA
International Classification:
G06K 9/62
G06V 10/56
Abstract:
The technology disclosed extracts intensities from sequencing images for base calling target clusters and attenuates spatial crosstalk from neighboring clusters. The technology disclosed accesses a particular section from a plurality of sections of an image output by a sensor, the particular section of the image including at least one pixel depicting intensity emission values from a target cluster and neighboring clusters located across the sensor, and convolves the particular section of the image with a corresponding convolution kernel in a plurality of convolution kernels, to generate a feature map comprising a plurality of feature values. The technology disclosed further assigns a corresponding feature value to the target cluster based on feature values in the plurality of feature values adjoining a center of the target cluster, and processes the corresponding feature value assigned to the target cluster, to base call the target cluster.

Increased Calculation Efficiency For Structured Illumination Microscopy

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US Patent:
20210118110, Apr 22, 2021
Filed:
Oct 21, 2020
Appl. No.:
17/075694
Inventors:
- San Diego CA, US
Andrew James YOUNG - San Diego CA, US
Andrew Dodge HEIBERG - San Diego CA, US
Bo LU - San Diego CA, US
Assignee:
Illumina, Inc. - San Diego CA
International Classification:
G06T 5/50
Abstract:
The technology disclosed relates to structured illumination microscopy (SIM). In particular, the technology disclosed relates to capturing and processing, in real time, numerous image tiles across a large image plane, dividing them into subtiles, efficiently processing the subtiles, and producing enhanced resolution images from the subtiles. The enhanced resolution images can be combined into enhanced images and can be used in subsequent analysis steps. The technology disclosed includes logic to reduce computing resources required to produce an enhanced resolution image from structured illumination of a target. A method is described for producing an enhanced resolution image from images of a target captured under structured illumination. This method applies one or more transformations to non-redundant data and then recovers redundant data from the non-redundant data after the transformations.

Method And Apparatus Of A Fully-Pipelined Layered Ldpc Decoder

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US Patent:
20190222227, Jul 18, 2019
Filed:
Feb 15, 2019
Appl. No.:
16/277890
Inventors:
- Culver City CA, US
Ricky Lap Kei Cheung - San Diego CA, US
Bo Lu - Carlsbad CA, US
International Classification:
H03M 13/11
Abstract:
Processors are arranged in a pipeline structure to operate on multiple layers of data, each layer comprising multiple groups of data. An input to a memory is coupled to an output of the last processor in the pipeline, and the memory's output is coupled to an input of the first processor in the pipeline. Multiplexing and de-multiplexing operations are performed in the pipeline. For each group in each layer, a stored result read from the memory is applied to the first processor in the pipeline structure. A calculated result of the stored result is output at the last processor and stored in the memory. Once processing for the last group of data in a first layer is completed, the corresponding processor is configured to process data in a next layer before the pipeline finishes processing the first layer. The stored result obtained from the next layer comprises a calculated result produced from a layer previous to the first layer.

Method And Apparatus Of A Fully-Pipelined Layered Ldpc Decoder

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US Patent:
20160173131, Jun 16, 2016
Filed:
Jan 29, 2016
Appl. No.:
15/011252
Inventors:
- Carlsbad CA, US
Ricky Lap Kei Cheung - San Diego CA, US
Bo Lu - Carlsbad CA, US
Assignee:
Tensorcom, Inc. - Carlsbad CA
International Classification:
H03M 13/11
Abstract:
Processors are arranged in a pipeline structure to operate on multiple layers of data, each layer comprising multiple groups of data. An input to a memory is coupled to an output of the last processor in the pipeline, and the memory's output is coupled to an input of the first processor in the pipeline. Multiplexing and de-multiplexing operations are performed in the pipeline. For each group in each layer, a stored result read from the memory is applied to the first processor in the pipeline structure. A calculated result of the stored result is output at the last processor and stored in the memory. Once processing for the last group of data in a first layer is completed, the corresponding processor is configured to process data in a next layer before the pipeline finishes processing the first layer. The stored result obtained from the next layer comprises a calculated result produced from a layer previous to the first layer.

Method And Apparatus Of A Fully-Pipelined Layered Ldpc Decoder

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US Patent:
20150214980, Jul 30, 2015
Filed:
Jan 27, 2014
Appl. No.:
14/165505
Inventors:
- Carlsbad CA, US
Ricky Lap Kei Cheung - Carlsbad CA, US
Bo Lu - Carlsbad CA, US
Assignee:
Tensorcom, Inc. - Carlsbad CA
International Classification:
H03M 13/11
Abstract:
The architecture is able to switch to Non-blocking check-node-update (CNU) scheduling architecture which has better performance than blocking CNU scheduling architecture. The architecture uses an Offset Min-Sum with Beta=1 with a clock domain operating at 440 MHz. The constraint macro-matrix is a spare matrix where each “1’ corresponds to a sub-array of a cyclically shifted identity matrix which is a shifted version of an identity matrix. Four core processors are used in the layered architecture where the constraint matrix uses a sub-array of 42 (check nodes)×42 (variable nodes) in the macro-array of 168×672 bits. Pipeline processing is used where the delay for each layer only requires 4 clock cycles.
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Bo Living Lu from San Diego, CA, age ~53 Get Report