Bo Liu

6552750, Apr 22, 2003

Mar 21, 2000

09/531392

Jeff Jang-Fang Suen - San Jose CA
Bo Liu - Fremont CA

TVIA, Inc. - Santa Clara CA

H04N 544

348561, 348565

A circuit for converting a selected portion of graphics data generated for a computer display for presentation on a selected portion of a television display including a first data path for transferring graphics data from a frame buffer memory storing graphics data to a television display without changing the size of the data, a second data path for transferring graphics data from the frame buffer memory storing graphics data to the television display while selectably changing the size of the data, the second data path including circuitry for selecting a portion of the television display to present the selected data transferred by the second data path, and zooming circuitry for enlarging data transferred by the second data path to fill the selected portion of the television display, and means for selecting data stored in the frame buffer for display.

8102705, Jan 24, 2012

Dec 10, 2009

12/635449

Bo Liu - Milpitas CA, US
Yan Li - Milpitas CA, US
Alexander Kwok-Tung Mak - Los Altos Hills CA, US
Chi-Ming Wang - Fremont CA, US
Eugene Jinglun Tam - Saratoga CA, US
Kwang-ho Kim - Pleasanton CA, US

SanDisk Technologies Inc. - Plano TX

G11C 16/04
G11C 7/10

36518503, 36518917, 36518905, 36518518, 714773, 714E11032

Techniques for the reading and writing of data in multi-state non-volatile memories are described. Data is written into the memory in a binary format, read into the data registers on the memory, and “folded” within the registers, and then written back into the memory in a multi-state format. In the folding operation, binary data from a single word line is folded into a multi-state format and, when rewritten in multi-state form, is written into a only a portion of another word line. A corresponding reading technique, where the data is “unfolded” is also described. The techniques further allow for the data to be encoded with an error correction code (ECC) on the controller that takes into account its eventual multi-state storage prior to transferring the data to the memory to be written in binary form. A register structure allowing such a “folding” operation is also presented. One set of embodiments include a local internal data bus that allows data to between the registers of different read/write stacks, where the internal bus can used in the internal data folding process.

8228729, Jul 24, 2012

Dec 21, 2011

13/333494

Bo Liu - Milpitas CA, US
Yan Li - Milpitas CA, US
Alexander Kwok-Tung Mak - Los Altos Hills CA, US
Chi-Ming Wang - Fremont CA, US
Eugene Jinglun Tam - Saratoga CA, US
Kwang-Ho Kim - Pleasanton CA, US

SanDisk Technologies Inc. - Plano TX

G11C 16/04
G11C 7/10

36518503, 36518917, 36518905, 36518518

Techniques for the reading and writing of data in multi-state non-volatile memories are described. Data is written into the memory in a binary format, read into the data registers on the memory, and “folded” within the registers, and then written back into the memory in a multi-state format. In the folding operation, binary data from a single word line is folded into a multi-state format and, when rewritten in multi-state form, is written into a only a portion of another word line. A corresponding reading technique, where the data is “unfolded” is also described. A register structure allowing such a “folding” operation is also presented. One set of embodiments include a local internal data bus that allows data to between the registers of different read/write stacks, where the internal bus can used in the internal data folding process.

8427884, Apr 23, 2013

Jun 20, 2011

13/164618

Bo Liu - Milpitas CA, US
Jongmin Park - Cupertino CA, US
Chen Chen - Mountain View CA, US
Tien-chien Kuo - Sunnyvale CA, US

SanDisk Technologies, Inc. - Plano TX

G11C 7/10

36518905, 36518518, 36518522, 36518523, 365189011, 36518916, 36518917, 36518907, 36518912

A circuit for counting in an N-bit string a number of bits M, having a first binary value includes N latch circuits in a daisy chain where each latch circuit has a tag bit that controls each to be either in a no-pass or pass state. Initially the tag bits are set according to the bits of the N-bit string where the first binary value corresponds to a no-pass state. A clock signal having a pulse train is run through the daisy chain to “interrogate” any no-pass latch circuits. It races right through any pass latch circuit. However, for a no-pass latch circuit, a leading pulse while being blocked also resets after a pulse period the tag bit from “no-pass” to “pass” state to allow subsequent pulses to pass. After all no-pass latch circuits have been reset, M is given by the number of missing pulses from the pulse train.

20130236582, Sep 12, 2013

Mar 7, 2012

13/414403

Bo Liu - Fremont CA, US

QUALMAT, INC. - Fremont CA

B22F 9/08

425 7

A gas atomization apparatus is disclosed for producing high purity fine refractory compound powders. After the system reaches high vacuum, a first stage inert atomizing gas breaks superheated metal melt into droplets and a second stage reactive atomizing gas breaks the droplets further into ultrafine droplets while reacts with them to form refractory compound powders. The first stage atomizing gas is inert gas able to break up melt into droplets and prevent crust formation on the nozzle front. A reaction time enhancer is arranged at bottom of reaction chamber to furnish a reactive gas flow in a reverse direction of the falling droplets and powders. Under the reverse gas flow, the falling droplets and powders change moving direction and travel longer distance in reaction chamber to increase reaction time. This apparatus can produce refractory powders with ultrahigh purity and uniform powder size while maintain high process energy efficiency.

20130294162, Nov 7, 2013

May 3, 2012

13/463422

Bo Liu - Milpitas CA, US
Frank Wanfang Tsai - Mountain View CA, US
Jongmin Park - Cupertino CA, US
Yan Li - Milpitas CA, US

G11C 16/06

36518509

In a non-volatile memory circuit, techniques are presented so that bad columns can be ignored and/or replaced during memory data input and output operations. A column redundant circuit for this purpose reduces circuit size and improves performance. User data is grouped in an interleaved manner so that data belonging to consecutive logical address will be distributed into different physical locations. For example, all column data can be physically grouped into, say, 5 divisions and user data can be written into or accessed from one division after another consecutively. Each division has its own clock control. The column redundancy block can generate bad column locations' information and send it to control logic to switch the user clock to a different division clock, thereby skipping bad columns. By controlling the clocks for different columns, the user can directly access good columns without touching bad columns.

20220325238, Oct 13, 2022

Mar 18, 2022

17/698636

- Stanford CA, US
Girija Dhamdhere - Stanford CA, US
Bo Liu - Palo Alto CA, US
Andrew A. Smith - Seattle WA, US
Alan W. Gomez - Lake Oswego OR, US

C12N 5/071
A61K 9/127
C07K 1/36
C07K 14/47
C07K 19/00
C12N 15/63

Provided herein are methods and culture systems for production of a biologically active Wnt polypeptide under a minimal serum condition. Also described herein include methods and culture systems for production of a biologically active Wnt polypeptide in a serum-free condition.

20200399588, Dec 24, 2020

Aug 18, 2020

16/996676

- La Jolla CA, US
Jill Helms - Portola Valley CA, US
Ying Zhu - Palo Alto CA, US
Bo Liu - Palo Alto CA, US
Stefanie Gaster - La Jolla CA, US

C12N 5/00
C07K 1/18
A61K 47/26
A61K 47/69
C12N 5/071

Disclosed herein are methods and compositions for producing a Wnt polypeptide under a serum-free condition. Also disclosed herein are methods of purifying the Wnt polypeptide from a serum-free condition.