Bin He Yu Yang

7537984, May 26, 2009

Dec 19, 2006

11/641507

Jeff D. Bude - Danville CA, US
Peide Ye - High Bridge NJ, US
Kwok K. Ng - Warren NJ, US
Bin Yang - Bridgewater NJ, US

Agere Systems Inc. - Allentown PA

H01L 21/338

438167, 438454, 438572, 257E21451

A field effect transistor configured for use in high power applications and a method for its fabrication is disclosed. The field effect transistor is formed of III-V materials and is configured to have a breakdown voltage that is advantageous for high power applications. The field effect transistor is so configured by determining the operating voltage and the desired breakdown voltage for that operating voltage. A peak electric field is then identified that is associated with the operating voltage and desired breakdown voltage. The device is then configured to exhibit the identified peak electric field at that operating voltage. The device is so configured by selecting device features that control the electrical potential in the device drift region is achieved. These features include the use of an overlapping gate or field plate in conjunction with a barrier layer overlying the device channel, or a p-type pocket formed in a region of single-crystal III-V material formed under the device channel. The overlapping gate/field plate or p-type pocket extend into the drift region of the device, controlling the electrical potential of the device in a manner that provides the desired control of the electrical potential in the drift region.

8236693, Aug 7, 2012

May 15, 2007

11/748743

Wen Yu - Freemont CA, US
Paul Besser - Sunnyvale CA, US
Bin Yang - Chappaqua NY, US
Haijiang Yu - Sunnyvale CA, US
Simon S. Chan - Saratoga CA, US

Advanced Micro Devices, Inc. - Sunnyvale CA

H01L 21/44

438682, 438210, 438655, 438660, 438761

The gate and active regions of a device are formed and alternating steps of applying and removing nitride and oxide layers allows exposing silicon in different areas while keeping silicon or polysilicon in other area covered with nitride. Metal layers are deposited over the exposed silicon or polysilicon and annealing forms a silicide layer in the selected exposed areas. The oxide and/or nitride layers are removed from the covered areas and another metal layer is deposited. The anneal process is repeated with silicide of one thickness formed over the second exposed areas with additional thickness of silicide formed over the previous silicide thickness.

8404589, Mar 26, 2013

Apr 6, 2010

12/754912

Andrew J. Kellock - Sunnyvale CA, US
Christian Lavoie - Pleasantville NY, US
Ahmet Ozcan - Pleasantville NY, US
Stephen Rossnagel - Pleasantville NY, US
Bin Yang - Ossining NY, US
Zhen Zhang - Ossining NY, US
Yu Zhu - West Harrison NY, US
Stefan Zollner - Hopewell Junction NY, US

International Business Machines Corporation - Armonk NY
Globalfoundries Inc.

H01L 21/44

438686, 438651, 438682, 438664, 438655, 257E21165

A method for forming a silicide contact includes depositing a metal layer on silicon such that the metal layer intermixes with the silicon to form an intermixed region on the silicon; removing an unintermixed portion of the metal layer from the intermixed region; and annealing the intermixed region to form a silicide contact on the silicon. A semiconductor device comprising a silicide contact located over a silicon layer of the semiconductor device, the silicide contact comprising nickel (Ni) and silicon (Si) and having Ni amount equivalent to a thickness of about 21 angstroms or less.

20120305940, Dec 6, 2012

Jun 1, 2011

13/151238

Thomas N. Adam - Slingerlands NY, US
Stephen W. Bedell - Wappingers Falls NY, US
Bruce B. Doris - Slingerlands NY, US
Lisa F. Edge - Watervliet NY, US
Keith E. Fogel - Hopewell Junction NY, US
Johnathan E. Faltermeier - Delanson NY, US
Jinghong Li - Poughquag NY, US
Alexander Reznicek - Troy NY, US
Devendra K. Sadana - Pleasantville NY, US
Bin Yang - Sunnyvale CA, US

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

H01L 29/24
H01L 21/20

257 77, 438481, 257E2109, 257E29104

A method and structure are disclosed for a defect free Si:C source/drain in an NFET device. A wafer is accepted with a primary surface of {100} crystallographic orientation. A recess is formed in the wafer in such manner that the bottom surface and the four sidewall surfaces of the recess are all having {100} crystallographic orientations. A Si:C material is eptaxially grown in the recess, and due to the crystallographic orientations the defect density next to each of the four sidewall surfaces is essentially the same as next to the bottom surface. The epitaxially filled recess is used in the source/drain fabrication of an NFET device. The NFET device is oriented along the crystallographic direction, and has the device channel under a tensile strain due to the defect free Si:C in the source/drain.

20130049199, Feb 28, 2013

Aug 31, 2011

13/222469

Paul R. Besser - Sunnyvale CA, US
Roy A. Carruthers - Stormville NY, US
Christopher P. D'Emic - Ossining NY, US
Christian Lavoie - Pleasantville NY, US
Conal E. Murray - Yorktown Heights NY, US
Kazuya Ohuchi - Kanagawa, JP
Christopher Scerbo - Bronx NY, US
Bin Yang - San Carlos CA, US

International Business Machines Corporation - Armonk NY

H01L 23/532
H01L 21/336
H01L 21/768

257741, 438682, 438305, 257E21575, 257E21409, 257E23157

Silicidation techniques with improved rare earth silicide morphology for fabrication of semiconductor device contacts. For example, a method for forming silicide includes implanting a silicon layer with an amorphizing species to form an amorphous silicon region in the silicon layer and depositing a rare earth metal film on the silicon layer in contact with the amorphous silicon region. A suicide process is then performed to combine the rare earth metal film and the amorphous silicon region to form a silicide film on the silicon layer.

20130049200, Feb 28, 2013

Aug 30, 2012

13/598686

Paul R. Besser - Sunnyvale CA, US
Roy A. Carruthers - Stormville NY, US
Christopher P. D'Emic - Ossining NY, US
Christian Lavoie - Pleasantville NY, US
Conal E. Murray - Yorktown Heights NY, US
Kazuya Ohuchi - Kanagawa, JP
Christopher Scerbo - Bronx NY, US
Bin Yang - San Carlos CA, US

International Business Machines Corporation - Armonk NY

H01L 29/43

257741, 257E29146

Silicidation techniques with improved rare earth silicide morphology for fabrication of semiconductor device contacts. For example, a method for forming silicide includes implanting a silicon layer with an amorphizing species to fond an amorphous silicon region in the silicon layer and depositing a rare earth metal film on the silicon layer in contact with the amorphous silicon region. A silicide process is then performed to combine the rare earth metal film and the amorphous silicon region to form a silicide film on the silicon layer.

20130069124, Mar 21, 2013

Sep 20, 2011

13/237732

Bin Yang - San Carlos CA, US
Christian Lavoie - Pleasantville NY, US
Emre Alptekin - Wappingers Falls NY, US
Ahmet S. Ozcan - Pleasantville NY, US
Cung D. Tran - Newburgh NY, US
Mark Raymond - Schenectady NY, US

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY
GLOBALFOUNDRIES INC. - Grand Cayman

H01L 29/78
H01L 21/20

257288, 438655, 257E21129, 257E29255

An MOSFET device having a Silicide layer of uniform thickness, and methods for its fabrication, are provided. One such method involves depositing a metal layer over wide and narrow contact trenches on the surface of a silicon semiconductor substrate. Upon formation of a uniformly thin amorphous intermixed alloy layer at the metal/silicon interface, the excess (unreacted) metal is removed. The device is annealed to facilitate the formation of a thin silicide layer on the substrate surface which exhibits uniform thickness at the bottoms of both wide and narrow contact trenches.

20140055152, Feb 27, 2014

Aug 24, 2012

13/594292

Amol Joshi - Sunnyvale CA, US
Charlene Chen - San Jose CA, US
John Foster - Mountain View CA, US
Zhendong Hong - San Jose CA, US
Olov Karlsson - San Jose CA, US
Bei Li - Fremont CA, US
Dipankar Pramanik - Saratoga CA, US
Usha Raghuram - Saratoga CA, US
Mark Victor Raymond - Schenectady NY, US
Jingang Su - Cupertino CA, US
Bin Yang - San Carlos CA, US

Globalfoundries, Inc. - Grand Cayman KY
Intermolecular, Inc. - San Jose CA

G01R 27/08

324720, 324691

Methods and structures are described for determining contact resistivities and Schottky barrier heights for conductors deposited on semiconductor wafers that can be combined with combinatorial processing, allowing thereby numerous processing conditions and materials to be tested concurrently. Methods for using multi-ring as well as single-ring CTLM structures to cancel parasitic resistance are also described, as well as structures and processes for inline monitoring of properties.