Bin Wang

7145203, Dec 5, 2006

Jul 2, 2004

10/884326

Bin Wang - Seattle WA, US

IMPINJ, Inc. - Seattle WA

H01L 29/78

257339, 257336, 257343, 257412

A high-voltage graded junction LDMOSFET includes a substrate of a first conductivity type, a well of the first conductivity type disposed in the substrate, a first region of a second conductivity type disposed in the well of the first conductivity type, a source terminal coupled to the first region of the second conductivity type, a well of the second conductivity type disposed in the substrate, a second region of the second conductivity type disposed in the well of the second conductivity type, a drain terminal coupled to the second region of the second conductivity type, a region of the first conductivity type disposed in the substrate, a body terminal coupled to the region of the first conductivity type, a graded-junction region formed of material of the first conductivity type separating the well of the first conductivity type and the well of the second conductivity type, the material of the first conductivity type in the graded-junction region doped at least an order of magnitude less than the wells, a dielectric layer disposed over the well of the first conductivity type, the graded-junction region and a portion of the well of the second conductivity type, a first isolator disposed in the well of the second conductivity type, the isolator including a dielectric material that is in contact with the dielectric layer, a second isolator disposed at least partially in the well of the second conductivity type, the second isolator including a dielectric material and isolating the second region of the second conductivity type from the region of the first conductivity type, and a gate disposed over the dielectric layer and a portion of the first isolator.

7257033, Aug 14, 2007

Mar 17, 2005

11/084214

Bin Wang - Seattle WA, US
Chih-Hsin Wang - San Jose CA, US
William T. Colleran - Seattle WA, US

Impinj, Inc. - Seattle WA

G11C 16/04

36518528, 36518529, 36518526, 36518517, 36518505

NVM arrays include rows and columns of NVM cells comprising a floating gate, dual transistor, inverter storage element. Supply voltage for selected storage elements is turned off during a programming and an erase mode. Isolation transistors for each NVM cell or for each row of NVM cells may be used to control the supply voltage.

7315067, Jan 1, 2008

Jul 2, 2004

10/884236

Bin Wang - Seattle WA, US

Impinj, Inc. - Seattle WA

H01L 29/43

257412, 257E2916

A native high-voltage n-channel LDMOSFET includes a p− doped substrate, a first n+ doped region disposed in the p− doped substrate, a source terminal coupled to the first n+ doped region, an n− well disposed in the substrate, a second n+ doped region disposed in the n− well, a drain terminal coupled to the second n+ doped region, a p+ doped region disposed in the substrate, a body terminal coupled to the p+ doped region, a dielectric layer disposed over the p− doped substrate and a portion of the n− well, a first trench disposed in the n− well, the trench filled with a dielectric material that is in contact with the dielectric layer, a second trench disposed at least partially in the n− well, the second trench filled with a dielectric material and isolating the second n+ region from the p+ region, and a gate partially or fully reversely doped with p+ implant (or an equivalent technique) and disposed over the dielectric layer and a portion of the first trench.

7375398, May 20, 2008

May 26, 2005

11/138888

Bin Wang - Seattle WA, US
Chih-Hsin Wang - San Jose CA, US

IMPINJ, Inc. - Seattle WA

H01L 23/62

257355, 257213, 257367, 257409, 257E29006, 438142

A FET device for operation at high voltages includes a substrate, a first well and a second well within the substrate that are doped with implants of a first type and second type, respectively. The first and second wells define a p-n junction. A field oxide layer within the second well defines a first surface region to receive a drain contact. A third well is located at least partially in the first well, includes doped implants of the second type, and is adapted to receive a source contact. As such, the third well defines a channel between itself and the second well within the first well. A gate is disposed over the channel. At least a first portion of the gate is disposed over the p-n junction, and includes doped implants of the first type. A number of permutations are allowed for doping the remainder of the gate.

7652921, Jan 26, 2010

Mar 31, 2008

12/080127

Andrew E. Horch - Seattle WA, US
Bin Wang - Seattle WA, US

Virage Logic Corporation - Fremont CA

G11C 16/04

3651851, 36518505

The present disclosure provides a Non-Volatile Memory (NVM) cell and programming method thereof. The cell can denote at least two logic levels. The cell has a read-transistor with a floating gate, and Band-To-Band-Tunneling device (BTBT device) sharing the floating gate with the read-transistor. The BTBT device is configured as an injection device for injecting a first charge onto the floating gate when the BTBT device is biased with a first gate bias voltage such that the BTBT device is in accumulation, to set at least one of the logic levels. A first electrode is coupled to bias the BTBT device with a first bias voltage that is higher than the first threshold voltage. The first bias voltage is controlled such that the BTBT device is in accumulation during a write operation. The injected amount of charge on the floating gate is determined by the first bias voltage.

7791950, Sep 7, 2010

May 15, 2007

11/748541

Bin Wang - Seattle WA, US
Shih-Hsin Wang - San Jose CA, US
William T. Colleran - Seattle WA, US

Virage Logic Corporation - Fremont CA

G11C 16/04

36518528, 36518529, 36518526, 36518517, 36518505

NVM arrays include rows and columns of NVM cells comprising a floating gate and a four transistor storage element. Supply voltage for selected storage elements is turned off during a programming and an erase mode. Isolation transistors for each NVM cell or for each row of NVM cells may be used to control the supply voltage.

8159001, Apr 17, 2012

Jul 19, 2006

11/490407

Bin Wang - Seattle WA, US

Synopsys, Inc. - Mountain View CA

H01L 29/72

257134, 257335, 257336, 257337, 257338, 257339, 257343, 257412

A graded junction space decreasing an implant concentration gradient between n-well and p-well regions of a semiconductor device is provided for enhancing breakdown voltage in high voltage applications. Split or unified FOX regions may be provided overlapping with the graded junction space. By using a p-well blocking layer to separate the p-well(s) and the n-well, breakdown voltage characteristic is improved without the cost of an additional mask or process change.

8264039, Sep 11, 2012

Sep 28, 2004

10/952708

Bin Wang - Seattle WA, US
William T. Colleran - Seattle WA, US
Chih-Hsin Wang - San Jose CA, US

Synopsys, Inc. - Mountain View CA

H01L 29/78

257339, 257335, 257409, 257397, 257E29256, 257E29268

A high-voltage LDMOSFET includes a semiconductor substrate, in which a gate well is formed. A source well and a drain well are formed on either side of the gate well, and include insulating regions within them that do not reach the full depth. An insulating layer is disposed on the substrate, covering the gate well and a portion of the source well and the drain well. A conductive gate is disposed on the insulating layer. Biasing wells are formed adjacent the source well and the drain well. A deep well is formed in the substrate such that it communicates with the biasing wells and the gate well, while extending under the source well and the drain well, such as to avoid them. Biasing contacts at the top of the biasing wells bias the deep well, and therefore also the gate well.